Bela

h1.  Nerdy notes 

This is just a collection of notes from/for developers. Sometimes it is also useful to know the mistakes that others made so not to waste your time when we already wasted ours. Note that if you attempt any of the hacks here it might void your warranty. Do not do this, please.

h2. Media clock on the Beaglebone Black with BeagleRT cape

The media clock is hardcoded to 44.1kHz. This can be changed by changing the PLL values in I2c_codec::startAudio.

Current settings are as follows

<pre>

writeRegister(0x02, 0x00)	// Codec sample rate register: fs_ref / 1

writeRegister(0x03, 0x91)	// PLL register A: PLL enabled, Q=2, P=1

writeRegister(0x04, 0x1C)	// PLL register B: J= 7

writeRegister(0x05, 0x52)	// PLL register C: D=5264, part 1

writeRegister(0x06, 0x40)	// PLL register D: D=5264, part 2

</pre>

Notes:

Q is not relevant as PLL is disabled 

J range is 1 to 63

D range is 0 to 9999

P range is 1 to 8

R range is 1 to 16

K=J.D=7.5264

P=1

R=1

PLLCLK_IN uses MCLK

CLKDIV_IN uses MCLK

PLLCLK is 12MHz

These values plugged in

  f_{S(ref)} = (PLLCLK_IN × K × R)/(2048 × P)

will give 44100

The media clock can be changed setting different values for J and D. As it is currently structured, the PRU loop does not allow you to get much faster than 48000kHz (J.D=K=8.1920) as you will start getting underruns.

As it turns out, on the BeagleRT cape the 12MHz clock is generated by the same master clock that drives the CPU, so these are going to be synced forever and ever (that is, do not expect any drift to occur between the media clock and the system clock).