diff dbg/dbg.py @ 29:83e80c2c489c

seperated working emu code from broken emu code.
wrote dbg interface

--- a/dbg/dbg.py	Fri Apr 11 14:38:09 2014 +0100
+++ b/dbg/dbg.py	Sun Apr 13 22:42:57 2014 +0100
@@ -2,89 +2,89 @@
 # dbg.py - debug client
 import struct
 import os, sys
-from subprocess import Popen, PIPE, STDOUT
+from time import sleep
 
-emu = Popen(['./a.out'], stdout=PIPE, stdin=PIPE, stderr=PIPE)
+# talks to the emulator
+# see dbgi() in emu/main.c for the inverse
+class controller:
+    
+    def __init__(self):
+        self.Emu = None
+        open('out', 'w').close()
+    
+    def snd(self, m):
+        self.Emu.stdin.write(struct.pack('>B', m))
 
-def snd(m):
-    emu.stdin.write(struct.pack('>B', m))
+    def rcv(self, l):
+        lc = 0
+        while lc != l:
+            lc = os.path.getsize('out')
+        sleep(0.5)
+        with open('out', 'r') as f:
+            c = f.read()
+        open('out', 'w').close()
+        return c
 
-def rcv():
-    with open('out', 'r') as f:
-        c = f.read()
-    return c
+    def step(self):
+        self.snd(0x00)
 
-def step():
-    snd(0x00)
+    def run(self, lenh, lenl):
+        self.snd(0x01)
+        snd(lenh)
+        snd(lenl)
 
-def run():
-    snd(0x01)
+    def set_reg(self, reg, data):
+        self.snd(0x02)
+        self.snd(reg)  # reg
+        self.snd(data) # data
 
-def set_reg(reg, data):
-    snd(0x02)
-    snd(reg)  # reg
-    snd(data) # data
+    def get_reg(self, reg):
+        self.snd(0x03)
+        self.snd(reg)  # reg
+        return self.rcv(1)
 
-def get_reg(reg):
-    snd(0x03)
-    snd(reg)  # reg
-    #return rcv()
+    def set_flag(self, flag, on):
+        self.snd(0x04)
+        if on == 0:
+            self.snd(flag)
+            self.snd(0)
+        else:
+            self.snd(flag)
+            self.snd(1)
 
-def set_flag(flag, on):
-    snd(0x04)
-    if on == 0:
-        snd(flag)
-        snd(0)
-    else:
-        snd(flag)
-        snd(1)
+    def get_flag(self, flag):
+        self.snd(0x05)
+        self.snd(flag)
+        return self.rcv(1)
 
-def get_flag(flag):
-    snd(0x05)
-    snd(flag)
-    #return rcv()
+    def set_block(self, addrh, addrl, data):
+        self.snd(0x06)
+        self.snd(addrh) # address high byte
+        self.snd(addrl) # address low byte
+        self.snd((len(data) >> 8) & 0xFF)
+        self.snd(len(data) & 0xFF)
+        for b in data:
+            self.snd(b) # data
 
-def set_block(addrh, addrl, lenh, lenl, data):
-    snd(0x06)
-    snd(addrh) # address high byte
-    snd(addrl) # address low byte
-    snd(lenh)
-    snd(lenl)
-    for b in data:
-        snd(b) # data
+    def get_block(self, addrh, addrl, lenh, lenl):
+        block = []
+        self.snd(0x07)
+        self.snd(addrh) # address high byte
+        self.snd(addrl) # address low byte
+        self.snd(lenh)  
+        self.snd(lenl) 
+        return self.rcv(lenl | (lenh << 8))
 
-def get_block(addrh, addrl, lenh, lenl):
-    block = []
-    snd(0x07)
-    snd(addrh) # address high byte
-    snd(addrl) # address low byte
-    snd(lenh)  
-    snd(lenl) 
-    #lc = 0
-    #while lc != l:
-    #    lc = os.path.getsize('out');
-    #return rcv()
+    def get_a(self):
+        self.snd(0x09)
+        return self.rcv(1)
 
-registers = {   
-        'r0':0,
-        'r1':1,
-        'r2':2,
-        'r3':3,
-        'dph':4,
-        'dpl':5,
-        'sph':6,
-        'spl':7,
-        'a':8,
-        'flags':9
-        }
+    def get_flags(self):
+        self.snd(0x0A)
+        return self.rcv(1)
 
-cmds = {
-        'step':step,
-        'run':run,
-        'sr':set_reg,
-        'gr':get_reg,
-        'sf':set_flag,
-        'gf':get_flag,
-        'sb':set_block,
-        'gb':get_block
-        }
+    def get_ir(self):
+        self.snd(0x0B)
+        return self.rcv(1)
+
+