comparison dbg/dbg.py @ 29:83e80c2c489c

seperated working emu code from broken emu code. wrote dbg interface
author james <jb302@eecs.qmul.ac.uk>
date Sun, 13 Apr 2014 22:42:57 +0100
parents 6d32e54e5c16
children 4411dee34085
comparison
equal deleted inserted replaced
28:6d32e54e5c16 29:83e80c2c489c
1 #!/usr/bin/env python 1 #!/usr/bin/env python
2 # dbg.py - debug client 2 # dbg.py - debug client
3 import struct 3 import struct
4 import os, sys 4 import os, sys
5 from subprocess import Popen, PIPE, STDOUT 5 from time import sleep
6 6
7 emu = Popen(['./a.out'], stdout=PIPE, stdin=PIPE, stderr=PIPE) 7 # talks to the emulator
8 # see dbgi() in emu/main.c for the inverse
9 class controller:
10
11 def __init__(self):
12 self.Emu = None
13 open('out', 'w').close()
14
15 def snd(self, m):
16 self.Emu.stdin.write(struct.pack('>B', m))
8 17
9 def snd(m): 18 def rcv(self, l):
10 emu.stdin.write(struct.pack('>B', m)) 19 lc = 0
20 while lc != l:
21 lc = os.path.getsize('out')
22 sleep(0.5)
23 with open('out', 'r') as f:
24 c = f.read()
25 open('out', 'w').close()
26 return c
11 27
12 def rcv(): 28 def step(self):
13 with open('out', 'r') as f: 29 self.snd(0x00)
14 c = f.read()
15 return c
16 30
17 def step(): 31 def run(self, lenh, lenl):
18 snd(0x00) 32 self.snd(0x01)
33 snd(lenh)
34 snd(lenl)
19 35
20 def run(): 36 def set_reg(self, reg, data):
21 snd(0x01) 37 self.snd(0x02)
38 self.snd(reg) # reg
39 self.snd(data) # data
22 40
23 def set_reg(reg, data): 41 def get_reg(self, reg):
24 snd(0x02) 42 self.snd(0x03)
25 snd(reg) # reg 43 self.snd(reg) # reg
26 snd(data) # data 44 return self.rcv(1)
27 45
28 def get_reg(reg): 46 def set_flag(self, flag, on):
29 snd(0x03) 47 self.snd(0x04)
30 snd(reg) # reg 48 if on == 0:
31 #return rcv() 49 self.snd(flag)
50 self.snd(0)
51 else:
52 self.snd(flag)
53 self.snd(1)
32 54
33 def set_flag(flag, on): 55 def get_flag(self, flag):
34 snd(0x04) 56 self.snd(0x05)
35 if on == 0: 57 self.snd(flag)
36 snd(flag) 58 return self.rcv(1)
37 snd(0)
38 else:
39 snd(flag)
40 snd(1)
41 59
42 def get_flag(flag): 60 def set_block(self, addrh, addrl, data):
43 snd(0x05) 61 self.snd(0x06)
44 snd(flag) 62 self.snd(addrh) # address high byte
45 #return rcv() 63 self.snd(addrl) # address low byte
64 self.snd((len(data) >> 8) & 0xFF)
65 self.snd(len(data) & 0xFF)
66 for b in data:
67 self.snd(b) # data
46 68
47 def set_block(addrh, addrl, lenh, lenl, data): 69 def get_block(self, addrh, addrl, lenh, lenl):
48 snd(0x06) 70 block = []
49 snd(addrh) # address high byte 71 self.snd(0x07)
50 snd(addrl) # address low byte 72 self.snd(addrh) # address high byte
51 snd(lenh) 73 self.snd(addrl) # address low byte
52 snd(lenl) 74 self.snd(lenh)
53 for b in data: 75 self.snd(lenl)
54 snd(b) # data 76 return self.rcv(lenl | (lenh << 8))
55 77
56 def get_block(addrh, addrl, lenh, lenl): 78 def get_a(self):
57 block = [] 79 self.snd(0x09)
58 snd(0x07) 80 return self.rcv(1)
59 snd(addrh) # address high byte
60 snd(addrl) # address low byte
61 snd(lenh)
62 snd(lenl)
63 #lc = 0
64 #while lc != l:
65 # lc = os.path.getsize('out');
66 #return rcv()
67 81
68 registers = { 82 def get_flags(self):
69 'r0':0, 83 self.snd(0x0A)
70 'r1':1, 84 return self.rcv(1)
71 'r2':2,
72 'r3':3,
73 'dph':4,
74 'dpl':5,
75 'sph':6,
76 'spl':7,
77 'a':8,
78 'flags':9
79 }
80 85
81 cmds = { 86 def get_ir(self):
82 'step':step, 87 self.snd(0x0B)
83 'run':run, 88 return self.rcv(1)
84 'sr':set_reg, 89
85 'gr':get_reg, 90
86 'sf':set_flag,
87 'gf':get_flag,
88 'sb':set_block,
89 'gb':get_block
90 }