annotate src/opus-1.3/celt/x86/x86cpu.c @ 169:223a55898ab9 tip default

Add null config files
author Chris Cannam <cannam@all-day-breakfast.com>
date Mon, 02 Mar 2020 14:03:47 +0000
parents 4664ac0c1032
children
rev   line source
cannam@154 1 /* Copyright (c) 2014, Cisco Systems, INC
cannam@154 2 Written by XiangMingZhu WeiZhou MinPeng YanWang
cannam@154 3
cannam@154 4 Redistribution and use in source and binary forms, with or without
cannam@154 5 modification, are permitted provided that the following conditions
cannam@154 6 are met:
cannam@154 7
cannam@154 8 - Redistributions of source code must retain the above copyright
cannam@154 9 notice, this list of conditions and the following disclaimer.
cannam@154 10
cannam@154 11 - Redistributions in binary form must reproduce the above copyright
cannam@154 12 notice, this list of conditions and the following disclaimer in the
cannam@154 13 documentation and/or other materials provided with the distribution.
cannam@154 14
cannam@154 15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
cannam@154 16 ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
cannam@154 17 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
cannam@154 18 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
cannam@154 19 OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
cannam@154 20 EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
cannam@154 21 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
cannam@154 22 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
cannam@154 23 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
cannam@154 24 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
cannam@154 25 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
cannam@154 26 */
cannam@154 27
cannam@154 28 #ifdef HAVE_CONFIG_H
cannam@154 29 #include "config.h"
cannam@154 30 #endif
cannam@154 31
cannam@154 32 #include "cpu_support.h"
cannam@154 33 #include "macros.h"
cannam@154 34 #include "main.h"
cannam@154 35 #include "pitch.h"
cannam@154 36 #include "x86cpu.h"
cannam@154 37
cannam@154 38 #if (defined(OPUS_X86_MAY_HAVE_SSE) && !defined(OPUS_X86_PRESUME_SSE)) || \
cannam@154 39 (defined(OPUS_X86_MAY_HAVE_SSE2) && !defined(OPUS_X86_PRESUME_SSE2)) || \
cannam@154 40 (defined(OPUS_X86_MAY_HAVE_SSE4_1) && !defined(OPUS_X86_PRESUME_SSE4_1)) || \
cannam@154 41 (defined(OPUS_X86_MAY_HAVE_AVX) && !defined(OPUS_X86_PRESUME_AVX))
cannam@154 42
cannam@154 43
cannam@154 44 #if defined(_MSC_VER)
cannam@154 45
cannam@154 46 #include <intrin.h>
cannam@154 47 static _inline void cpuid(unsigned int CPUInfo[4], unsigned int InfoType)
cannam@154 48 {
cannam@154 49 __cpuid((int*)CPUInfo, InfoType);
cannam@154 50 }
cannam@154 51
cannam@154 52 #else
cannam@154 53
cannam@154 54 #if defined(CPU_INFO_BY_C)
cannam@154 55 #include <cpuid.h>
cannam@154 56 #endif
cannam@154 57
cannam@154 58 static void cpuid(unsigned int CPUInfo[4], unsigned int InfoType)
cannam@154 59 {
cannam@154 60 #if defined(CPU_INFO_BY_ASM)
cannam@154 61 #if defined(__i386__) && defined(__PIC__)
cannam@154 62 /* %ebx is PIC register in 32-bit, so mustn't clobber it. */
cannam@154 63 __asm__ __volatile__ (
cannam@154 64 "xchg %%ebx, %1\n"
cannam@154 65 "cpuid\n"
cannam@154 66 "xchg %%ebx, %1\n":
cannam@154 67 "=a" (CPUInfo[0]),
cannam@154 68 "=r" (CPUInfo[1]),
cannam@154 69 "=c" (CPUInfo[2]),
cannam@154 70 "=d" (CPUInfo[3]) :
cannam@154 71 "0" (InfoType)
cannam@154 72 );
cannam@154 73 #else
cannam@154 74 __asm__ __volatile__ (
cannam@154 75 "cpuid":
cannam@154 76 "=a" (CPUInfo[0]),
cannam@154 77 "=b" (CPUInfo[1]),
cannam@154 78 "=c" (CPUInfo[2]),
cannam@154 79 "=d" (CPUInfo[3]) :
cannam@154 80 "0" (InfoType)
cannam@154 81 );
cannam@154 82 #endif
cannam@154 83 #elif defined(CPU_INFO_BY_C)
cannam@154 84 __get_cpuid(InfoType, &(CPUInfo[0]), &(CPUInfo[1]), &(CPUInfo[2]), &(CPUInfo[3]));
cannam@154 85 #endif
cannam@154 86 }
cannam@154 87
cannam@154 88 #endif
cannam@154 89
cannam@154 90 typedef struct CPU_Feature{
cannam@154 91 /* SIMD: 128-bit */
cannam@154 92 int HW_SSE;
cannam@154 93 int HW_SSE2;
cannam@154 94 int HW_SSE41;
cannam@154 95 /* SIMD: 256-bit */
cannam@154 96 int HW_AVX;
cannam@154 97 } CPU_Feature;
cannam@154 98
cannam@154 99 static void opus_cpu_feature_check(CPU_Feature *cpu_feature)
cannam@154 100 {
cannam@154 101 unsigned int info[4] = {0};
cannam@154 102 unsigned int nIds = 0;
cannam@154 103
cannam@154 104 cpuid(info, 0);
cannam@154 105 nIds = info[0];
cannam@154 106
cannam@154 107 if (nIds >= 1){
cannam@154 108 cpuid(info, 1);
cannam@154 109 cpu_feature->HW_SSE = (info[3] & (1 << 25)) != 0;
cannam@154 110 cpu_feature->HW_SSE2 = (info[3] & (1 << 26)) != 0;
cannam@154 111 cpu_feature->HW_SSE41 = (info[2] & (1 << 19)) != 0;
cannam@154 112 cpu_feature->HW_AVX = (info[2] & (1 << 28)) != 0;
cannam@154 113 }
cannam@154 114 else {
cannam@154 115 cpu_feature->HW_SSE = 0;
cannam@154 116 cpu_feature->HW_SSE2 = 0;
cannam@154 117 cpu_feature->HW_SSE41 = 0;
cannam@154 118 cpu_feature->HW_AVX = 0;
cannam@154 119 }
cannam@154 120 }
cannam@154 121
cannam@154 122 int opus_select_arch(void)
cannam@154 123 {
cannam@154 124 CPU_Feature cpu_feature;
cannam@154 125 int arch;
cannam@154 126
cannam@154 127 opus_cpu_feature_check(&cpu_feature);
cannam@154 128
cannam@154 129 arch = 0;
cannam@154 130 if (!cpu_feature.HW_SSE)
cannam@154 131 {
cannam@154 132 return arch;
cannam@154 133 }
cannam@154 134 arch++;
cannam@154 135
cannam@154 136 if (!cpu_feature.HW_SSE2)
cannam@154 137 {
cannam@154 138 return arch;
cannam@154 139 }
cannam@154 140 arch++;
cannam@154 141
cannam@154 142 if (!cpu_feature.HW_SSE41)
cannam@154 143 {
cannam@154 144 return arch;
cannam@154 145 }
cannam@154 146 arch++;
cannam@154 147
cannam@154 148 if (!cpu_feature.HW_AVX)
cannam@154 149 {
cannam@154 150 return arch;
cannam@154 151 }
cannam@154 152 arch++;
cannam@154 153
cannam@154 154 return arch;
cannam@154 155 }
cannam@154 156
cannam@154 157 #endif