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1 Performance Counters
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2 ====================
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3
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4 FFTW measures execution time in the planning stage, optionally taking advantage
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5 of hardware performance counters. This document describes the supported
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6 counters and additional steps needed to enable each on different architectures.
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7
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8 See `./configure --help` for flags for enabling each supported counter.
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9 See [kernel/cycle.h](kernel/cycle.h) for the code that accesses the counters.
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10
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11 ARMv7-A (armv7a)
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12 ================
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13
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14 `CNTVCT`: Virtual Count Register in VMSA
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15 --------------------------------------
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16
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17 A 64-bit counter part of Virtual Memory System Architecture.
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18 Section B4.1.34 in ARM Architecture Reference Manual ARMv7-A/ARMv7-R
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19
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20 For access from user mode, requires `CNTKCTL.PL0VCTEN == 1`, which must
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21 be set in kernel mode on each CPU:
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22
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23 #define CNTKCTL_PL0VCTEN 0x2 /* B4.1.26 in ARM Architecture Rreference */
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24 uint32_t r;
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25 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r"(r)); /* read */
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26 r |= CNTKCTL_PL0VCTEN;
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27 asm volatile("mcr p15, 0, %0, c14, c1, 0" :: "r"(r)); /* write */
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28
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29 Kernel module source *which can be patched with the above code* available at:
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30 https://github.com/thoughtpolice/enable_arm_pmu
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31
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32 `PMCCNTR`: Performance Monitors Cycle Count Register in VMSA
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33 ----------------------------------------------------------
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34
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35 A 32-bit counter part of Virtual Memory System Architecture.
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36 Section B4.1.113 in ARM Architecture Reference Manual ARMv7-A/ARMv7-R
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37
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38 For access from user mode, requires user-mode access to PMU to be enabled
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39 (`PMUSERENR.EN == 1`), which must be done from kernel mode on each CPU:
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40
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41 #define PERF_DEF_OPTS (1 | 16)
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42 /* enable user-mode access to counters */
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43 asm volatile("mcr p15, 0, %0, c9, c14, 0" :: "r"(1));
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44 /* Program PMU and enable all counters */
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45 asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(PERF_DEF_OPTS));
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46 asm volatile("mcr p15, 0, %0, c9, c12, 1" :: "r"(0x8000000f));
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47
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48 Kernel module source with the above code available at:
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49 [GitHub thoughtpolice/enable\_arm\_pmu](https://github.com/thoughtpolice/enable_arm_pmu)
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50
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51 More information:
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52 http://neocontra.blogspot.com/2013/05/user-mode-performance-counters-for.html
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53
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54 ARMv8-A (aarch64)
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55 =================
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56
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57 `CNTVCT_EL0`: Counter-timer Virtual Count Register
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58 ------------------------------------------------
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59
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60 A 64-bit counter, part of Generic Registers.
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61 Section D8.5.17 in ARM Architecture Reference Manual ARMv8-A
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62
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63 For user-mode access, requires `CNTKCTL_EL1.EL0VCTEN == 1`, which
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64 must be set from kernel mode for each CPU:
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65
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66 #define CNTKCTL_EL0VCTEN 0x2
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67 uint32_t r;
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68 asm volatile("mrs %0, CNTKCTL_EL1" : "=r"(r)); /* read */
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69 r |= CNTKCTL_EL0VCTEN;
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70 asm volatile("msr CNTKCTL_EL1, %0" :: "r"(r)); /* write */
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71
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72 *WARNING*: Above code was not tested.
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73
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74 `PMCCNTR_EL0`: Performance Monitors Cycle Count Register
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75 ------------------------------------------------------
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76
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77 A 64-bit counter, part of Performance Monitors.
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78 Section D8.4.2 in ARM Architecture Reference Manual ARMv8-A
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79
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80 For access from user mode, requires user-mode access to PMU (`PMUSERENR_EL0.EN
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81 == 1`), which must be set from kernel mode for each CPU:
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82
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83 #define PERF_DEF_OPTS (1 | 16)
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84 /* enable user-mode access to counters */
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85 asm volatile("msr PMUSERENR_EL0, %0" :: "r"(1));
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86 /* Program PMU and enable all counters */
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87 asm volatile("msr PMCR_EL0, %0" :: "r"(PERF_DEF_OPTS));
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88 asm volatile("msr PMCNTENSET_EL0, %0" :: "r"(0x8000000f));
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89 asm volatile("msr PMCCFILTR_EL0, %0" :: "r"(0));
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90
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91 Kernel module source with the above code available at:
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92 [GitHub rdolbeau/enable\_arm\_pmu](https://github.com/rdolbeau/enable_arm_pmu)
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93 or in [Pull Request #2 at thoughtpolice/enable\_arm\_pmu](https://github.com/thoughtpolice/enable_arm_pmu/pull/2)
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