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| author | james <jb302@eecs.qmul.ac.uk> |
|---|---|
| date | Tue, 22 Apr 2014 14:25:14 +0100 |
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ELB816 instruction set V1.0 Dec HEX Binary Mnemonic Register transfer description Comments 0 00 00000000 NOP PC = PC+1 No Operation 1 01 00000001 reserved currently unallocated opcode - treat as NOP 2 02 00000010 reserved currently unallocated opcode - treat as NOP 3 03 00000011 reserved currently unallocated opcode - treat as NOP 4 04 00000100 reserved currently unallocated opcode - treat as NOP 5 05 00000101 reserved currently unallocated opcode - treat as NOP 6 06 00000110 reserved currently unallocated opcode - treat as NOP 7 07 00000111 reserved currently unallocated opcode - treat as NOP 8 08 00001000 SET C 1 -> CY Set carry bit to 1 9 09 00001001 CLR C 0 -> CY Set carry bit to 0 10 0A 00001010 SET BS 1 -> BS Switch to register bank 1 11 0B 00001011 CLR BS 0 -> BS Switch to register bank 0 12 0C 00001100 SET IE 1 -> IE Enable interrupts 13 0D 00001101 CLR IE 0 -> IE Disable interrupts 14 0E 00001110 CPL C not CY -> CY Complement carry bit 15 0F 00001111 CPL A not A -> A Complement accumulator 16 10 00010000 XCSD SP -> DPTR : DPTR -> SP Exchange SP with DPTR 17 11 00010001 SFA FLAGS -> A store flags to accumulator 18 12 00010010 LAF A -> FLAGS load accumulator to flags 19 13 00010011 MOV DPTR, SP SP -> DPTR move word SP to DPTR 20 14 00010100 MOV SP, DPTR DPTR -> SP move word DPTR to SP 21 15 00010101 MOV A, #data8 data8 -> A move immediate byte to accumulator 22 16 00010110 MOV SP, #data16 data16 -> SP move immediate word to SP 23 17 00010111 MOV DPTR, #data16 data16 -> DPTR move immediate word to DPTR 24 18 00011000 MOV A, addr16 main[addr16] -> A move data from direct address to accumulator 25 19 00011001 MOV addr16, A A -> main[addr16] move data from accumulator to direct address 26 1A 00011010 MOV A, @A+DPTR main[DPTR+A] -> A indexed move relative to DPTR to accumulator 27 1B 00011011 MOV A, @A+PC main[PC+A] -> A indexed move relative to PC to accumulator 28 1C 00011100 MOV A, @addr16 main[main[addr16]] -> A move data from indirect address to accumulator 29 1D 00011101 MOV @addr16, A A -> main[main[addr16]] move data from accumulator to indirect address 30 1E 00011110 MOV A, @DPTR main[DPTR] -> A register indirect move to accumulator 31 1F 00011111 MOV @DPTR, A A -> main[DPTR] register indirect move from accumulator 32 20 00100000 MOV @DPTR, R0 R0 -> main[DPTR] 33 21 00100001 MOV @DPTR, R1 R1 -> main[DPTR] 34 22 00100010 MOV @DPTR, R2 R2 -> main[DPTR] 35 23 00100011 MOV @DPTR, R3 R3 -> main[DPTR] 36 24 00100100 MOV @DPTR, DPH DPH -> main[DPTR] 37 25 00100101 MOV @DPTR, DPL DPL -> main[DPTR] 38 26 00100110 MOV @DPTR, SPH SPH -> main[DPTR] 39 27 00100111 MOV @DPTR, SPL SPL -> main[DPTR] 40 28 00101000 MOV R0, #data8 data8 -> R0 41 29 00101001 MOV R1, #data8 data8 -> R1 42 2A 00101010 MOV R2, #data8 data8 -> R2 43 2B 00101011 MOV R3, #data8 data8 -> R3 44 2C 00101100 MOV DPH, #data8 data8 -> DPH 45 2D 00101101 MOV DPL, #data8 data8 -> DPL 46 2E 00101110 MOV SPH, #data8 data8 -> SPH 47 2F 00101111 MOV SPL, #data8 data8 -> SPL 48 30 00110000 MOV R0, A A -> R0 49 31 00110001 MOV R1, A A -> R1 50 32 00110010 MOV R2, A A -> R2 51 33 00110011 MOV R3, A A -> R3 52 34 00110100 MOV DPH, A A -> DPH 53 35 00110101 MOV DPL, A A -> DPL 54 36 00110110 MOV SPH, A A -> SPH 55 37 00110111 MOV SPL, A A -> SPL 56 38 00111000 MOV A, R0 R0 -> A 57 39 00111001 MOV A, R1 R1 -> A 58 3A 00111010 MOV A, R2 R2 -> A 59 3B 00111011 MOV A, R3 R3 -> A 60 3C 00111100 MOV A, DPH DPH -> A 61 3D 00111101 MOV A, DPL DPL -> A 62 3E 00111110 MOV A, SPH SPH -> A 63 3F 00111111 MOV A, SPL SPL -> A 64 40 01000000 MOV R0, @DPTR main[DPTR] -> R0 65 41 01000001 MOV R0, R1 R1 -> R0 66 42 01000010 MOV R0, R2 R2 -> R0 67 43 01000011 MOV R0, R3 R3 -> R0 68 44 01000100 MOV R0, DPH DPH -> R0 69 45 01000101 MOV R0, DPL DPL -> R0 70 46 01000110 MOV R0, SPH SPH -> R0 71 47 01000111 MOV R0, SPL SPL -> R0 72 48 01001000 MOV R1, R0 R0 -> R1 73 49 01001001 MOV R1, @DPTR main[DPTR] -> R1 74 4A 01001010 MOV R1, R2 R2 -> R1 75 4B 01001011 MOV R1, R3 R3 -> R1 76 4C 01001100 MOV R1, DPH DPH -> R1 77 4D 01001101 MOV R1, DPL DPL -> R1 78 4E 01001110 MOV R1, SPH SPH -> R1 79 4F 01001111 MOV R1, SPL SPL -> R1 80 50 01010000 MOV R2, R0 R0 -> R2 81 51 01010001 MOV R2, R1 R1 -> R2 82 52 01010010 MOV R2, @DPTR main[DPTR] -> R2 83 53 01010011 MOV R2, R3 R3 -> R2 84 54 01010100 MOV R2, DPH DPH -> R2 85 55 01010101 MOV R2, DPL DPL -> R2 86 56 01010110 MOV R2, SPH SPH -> R2 87 57 01010111 MOV R2, SPL SPL -> R2 88 58 01011000 MOV R3, R0 R0 -> R3 89 59 01011001 MOV R3, R1 R1 -> R3 90 5A 01011010 MOV R3, R2 R2 -> R3 91 5B 01011011 MOV R3, @DPTR main[DPTR] -> R3 92 5C 01011100 MOV R3, DPH DPH -> R3 93 5D 01011101 MOV R3, DPL DPL -> R3 94 5E 01011110 MOV R3, SPH SPH -> R3 95 5F 01011111 MOV R3, SPL SPL -> R3 96 60 01100000 MOV DPH, R0 R0 -> DPH 97 61 01100001 MOV DPH, R1 R1 -> DPH 98 62 01100010 MOV DPH, R2 R2 -> DPH 99 63 01100011 MOV DPH, R3 R3 -> DPH 100 64 01100100 MOV DPH, @DPTR main[DPTR] -> DPH 101 65 01100101 MOV DPH, DPL DPL -> DPH 102 66 01100110 MOV DPH, SPH SPH -> DPH 103 67 01100111 MOV DPH, SPL SPL -> DPH 104 68 01101000 MOV DPL, R0 R0 -> DPL 105 69 01101001 MOV DPL, R1 R1 -> DPL 106 6A 01101010 MOV DPL, R2 R2 -> DPL 107 6B 01101011 MOV DPL, R3 R3 -> DPL 108 6C 01101100 MOV DPL, DPH DPH -> DPL 109 6D 01101101 MOV DPL, @DPTR main[DPTR] -> DPL 110 6E 01101110 MOV DPL, SPH SPH -> DPL 111 6F 01101111 MOV DPL, SPL SPL -> DPL 112 70 01110000 MOV SPH, R0 R0 -> SPH 113 71 01110001 MOV SPH, R1 R1 -> SPH 114 72 01110010 MOV SPH, R2 R2 -> SPH 115 73 01110011 MOV SPH, R3 R3 -> SPH 116 74 01110100 MOV SPH, DPH DPH -> SPH 117 75 01110101 MOV SPH, DPL DPL -> SPH 118 76 01110110 MOV SPH, @DPTR main[DPTR] -> SPH 119 77 01110111 MOV SPH, SPL SPL -> SPH 120 78 01111000 MOV SPL, R0 R0 -> SPL 121 79 01111001 MOV SPL, R1 R1 -> SPL 122 7A 01111010 MOV SPL, R2 R2 -> SPL 123 7B 01111011 MOV SPL, R3 R3 -> SPL 124 7C 01111100 MOV SPL, DPH DPH -> SPL 125 7D 01111101 MOV SPL, DPL DPL -> SPL 126 7E 01111110 MOV SPL, SPH SPH -> SPL 127 7F 01111111 MOV SPL, @DPTR main[DPTR] -> SPL 128 80 10000000 ANL A, R0 A and R0 -> A 129 81 10000001 ANL A, R1 A and R1 -> A 130 82 10000010 ANL A, R2 A and R2 -> A 131 83 10000011 ANL A, R3 A and R3 -> A 132 84 10000100 ANL A, DPH A and DPH -> A 133 85 10000101 ANL A, DPL A and DPL -> A 134 86 10000110 ANL A, #data8 A and data8 -> A 135 87 10000111 ANL A, @DPTR A and main[DPTR] -> A 136 88 10001000 ORL A, R0 A or R0 -> A 137 89 10001001 ORL A, R1 A or R1 -> A 138 8A 10001010 ORL A, R2 A or R2 -> A 139 8B 10001011 ORL A, R3 A or R3 -> A 140 8C 10001100 ORL A, DPH A or DPH -> A 141 8D 10001101 ORL A, DPL A or DPL -> A 142 8E 10001110 ORL A, #data8 A or data8 -> A 143 8F 10001111 ORL A, @DPTR A or main[DPTR] -> A 144 90 10010000 XRL A, R0 A xor R0 -> A 145 91 10010001 XRL A, R1 A xor R1 -> A 146 92 10010010 XRL A, R2 A xor R2 -> A 147 93 10010011 XRL A, R3 A xor R3 -> A 148 94 10010100 XRL A, DPH A xor DPH -> A 149 95 10010101 XRL A, DPL A xor DPL -> A 150 96 10010110 XRL A, #data8 A xor data8 -> A 151 97 10010111 XRL A, @DPTR A xor main[DPTR] -> A 152 98 10011000 RL A rotate accumulator left 153 99 10011001 RLC A rotate accumulator left through carry 154 9A 10011010 RR A rotate accumulator right 155 9B 10011011 RRC A rotate accumulator right through carry 156 9C 10011100 INC DPTR DPTR + 1 -> DPTR Increment DPTR 157 9D 10011101 DEC DPTR DPTR -1 -> DPTR Decrement DPTR 158 9E 10011110 INC A A + 1 -> A Increment accumulator 159 9F 10011111 DEC A A - 1 -> A Decrement accumulator 160 A0 10100000 ADD A, R0 A + R0 -> A 161 A1 10100001 ADD A, R1 A + R1 -> A 162 A2 10100010 ADD A, R2 A + R2 -> A 163 A3 10100011 ADD A, R3 A + R3 -> A 164 A4 10100100 ADD A, DPH A + DPH -> A 165 A5 10100101 ADD A, DPL A + DPL -> A 166 A6 10100110 ADD A, #data8 A + data8 -> A 167 A7 10100111 ADD A, @DPTR A + main[DPTR] -> A 168 A8 10101000 ADDC A, R0 A + R0 + CY -> A 169 A9 10101001 ADDC A, R1 A + R1 + CY -> A 170 AA 10101010 ADDC A, R2 A + R2 + CY -> A 171 AB 10101011 ADDC A, R3 A + R3 + CY -> A 172 AC 10101100 ADDC A, DPH A + DPH + CY -> A 173 AD 10101101 ADDC A, DPL A + DPL + CY -> A 174 AE 10101110 ADDC A, #data8 A + data8 + CY -> A 175 AF 10101111 ADDC A, @DPTR A + main[DPTR] + CY -> A 176 B0 10110000 SUB A, R0 A - R0 -> A 177 B1 10110001 SUB A, R1 A - R1 -> A 178 B2 10110010 SUB A, R2 A - R2 -> A 179 B3 10110011 SUB A, R3 A - R3 -> A 180 B4 10110100 SUB A, DPH A - DPH -> A 181 B5 10110101 SUB A, DPL A - DPL -> A 182 B6 10110110 SUB A, #data8 A - data8 -> A 183 B7 10110111 SUB A, @DPTR A - main[DPTR] -> A 184 B8 10111000 SUBB A, R0 A - R0 - CY -> A 185 B9 10111001 SUBB A, R1 A - R1 - CY -> A 186 BA 10111010 SUBB A, R2 A - R2 - CY -> A 187 BB 10111011 SUBB A, R3 A - R3 - CY -> A 188 BC 10111100 SUBB A, DPH A - DPH - CY -> A 189 BD 10111101 SUBB A, DPL A - DPL - CY -> A 190 BE 10111110 SUBB A, #data8 A - data8 - CY -> A 191 BF 10111111 SUBB A, @DPTR A - main[DPTR] - CY -> A 192 C0 11000000 PJMP addr11 Page Jump [PC(15:11) 0 0 0 addr8] 193 C1 11000001 PJMP addr11 Page Jump [PC(15:11) 0 0 1 addr8] 194 C2 11000010 PJMP addr11 Page Jump [PC(15:11) 0 1 0 addr8] 195 C3 11000011 PJMP addr11 Page Jump [PC(15:11) 0 1 1 addr8] 196 C4 11000100 PJMP addr11 Page Jump [PC(15:11) 1 0 0 addr8] 197 C5 11000101 PJMP addr11 Page Jump [PC(15:11) 1 0 1 addr8] 198 C6 11000110 PJMP addr11 Page Jump [PC(15:11) 1 1 0 addr8] 199 C7 11000111 PJMP addr11 Page Jump [PC(15:11) 1 1 1 addr8] 200 C8 11001000 PCALL addr11 Page Call [PC(15:11) 0 0 0 addr8] 201 C9 11001001 PCALL addr11 Page Call [PC(15:11) 0 0 1 addr8] 202 CA 11001010 PCALL addr11 Page Call [PC(15:11) 0 1 0 addr8] 203 CB 11001011 PCALL addr11 Page Call [PC(15:11) 0 1 1 addr8] 204 CC 11001100 PCALL addr11 Page Call [PC(15:11) 1 0 0 addr8] 205 CD 11001101 PCALL addr11 Page Call [PC(15:11) 1 0 1 addr8] 206 CE 11001110 PCALL addr11 Page Call [PC(15:11) 1 1 0 addr8] 207 CF 11001111 PCALL addr11 Page Call [PC(15:11) 1 1 1 addr8] 208 D0 11010000 DJNZ R0, rel8 Decrement R0 and jump if not zero 209 D1 11010001 DJNZ R1, rel8 Decrement R1 and jump if not zero 210 D2 11010010 DJNZ R2, rel8 Decrement R2 and jump if not zero 211 D3 11010011 DJNZ R3, rel8 Decrement R3 and jump if not zero 212 D4 11010100 CJNE R0, #data, rel8 Compare R0 with data8 and jump if not equal 213 D5 11010101 CJNE R1, #data, rel8 Compare R1 with data8 and jump if not equal 214 D6 11010110 CJNE R2, #data, rel8 Compare R2 with data8 and jump if not equal 215 D7 11010111 CJNE R3, #data, rel8 Compare R3 with data8 and jump if not equal 216 D8 11011000 LJMP addr16 Long jump to addr16 217 D9 11011001 LCALL addr16 Long call to subroutine at addr16 218 DA 11011010 RET return from subroutine 219 DB 11011011 RETI return from interrupt 220 DC 11011100 SJMP rel8 short (relative) jump 221 DD 11011101 JMP @A+DPTR Indexed indirect jump relative to DPTR 222 DE 11011110 JMP @DPTR jump indirect to DPTR 223 DF 11011111 CJNE A, #data8, rel8 Compare A with data8 and jump if not equal 224 E0 11100000 JZ rel8 Jump if zero 225 E1 11100001 JNZ rel8 Jump if not zero 226 E2 11100010 JC rel8 Jump if carry 227 E3 11100011 JNC rel8 Jump if not carry 228 E4 11100100 JPO rel8 Jump if parity odd 229 E5 11100101 JPE rel8 Jump if parity even 230 E6 11100110 JS rel8 Jump if sign (negative) 231 E7 11100111 JNS rel8 Jump if not sign (positive) 232 E8 11101000 PUSH R0 Push R0 to the stack 233 E9 11101001 PUSH R1 Push R1 to the stack 234 EA 11101010 PUSH R2 Push R2 to the stack 235 EB 11101011 PUSH R3 Push R3 to the stack 236 EC 11101100 PUSH DPH Push DPH to the stack 237 ED 11101101 PUSH DPL Push DPL to the stack 238 EE 11101110 PUSH A Push Accumulator to the stack 239 EF 11101111 PUSH FLAGS Push Flags register to the stack 240 F0 11110000 POP R0 Pop top off stack to R0 241 F1 11110001 POP R1 Pop top off stack to R1 242 F2 11110010 POP R2 Pop top off stack to R2 243 F3 11110011 POP R3 Pop top off stack to R3 244 F4 11110100 POP DPH Pop top off stack to DPH 245 F5 11110101 POP DPL Pop top off stack to DPL 246 F6 11110110 POP A Pop top off stack to Accumulator 247 F7 11110111 POP FLAGS Pop top off stack to Flags register 248 F8 11111000 MUL R0, R1 R0 * R1 -> {R0 R1} unsigned integer multiply R0 by R1, 16-bit result left in R0 and R1, R0 holds most significant byte 249 F9 11111001 DIV R0, R1 R0 / R1 -> {R0 R1} unsigned integer division R0 by R1, 16-bit result left in R0 and R1, R0 holds most significant byte 250 FA 11111010 DA A Decimal adjust accumulator 251 FB 11111011 reserved currently unallocated opcode - treat as NOP 252 FC 11111100 IN A, port_addr Input value on I/O port 'port_addr' to accumulator 253 FD 11111101 OUT port_addr, A Output accumulator value to I/O port 'port_addr' 254 FE 11111110 INT vect8 Software interrupt at vector vect8 255 FF 11111111 HLT Halt processor