annotate emu/mem.c @ 29:83e80c2c489c

seperated working emu code from broken emu code. wrote dbg interface
author james <jb302@eecs.qmul.ac.uk>
date Sun, 13 Apr 2014 22:42:57 +0100
parents 6d32e54e5c16
children c0c2e99b6bb0
rev   line source
jb302@28 1 /* mem.c
jb302@28 2 * functions for accessing emulator memory */
jb302@28 3 #include "mem.h"
jb302@28 4
jb302@28 5 /* get flag value
jb302@28 6 * if invalid flag is requested value is 0 */
jb302@28 7 BYTE
jb302@28 8 get_flag(BYTE flag) {
jb302@28 9 if (flag > 7) {
jb302@28 10 return 0;
jb302@28 11 }
jb302@28 12 else {
jb302@28 13 return GBIT(flags, flag);
jb302@28 14 }
jb302@28 15 }
jb302@28 16
jb302@28 17 /* set flag to 0 if on == 0
jb302@28 18 * otherwise set flag to 1 */
jb302@28 19 void
jb302@28 20 set_flag(BYTE flag, BYTE on) {
jb302@28 21 if (flag <= 7) {
jb302@29 22 if (on == 0x00) {
jb302@29 23 flags = CBIT(flags, flag);
jb302@29 24 }
jb302@29 25 else {
jb302@29 26 flags = SBIT(flags, flag);
jb302@28 27 }
jb302@28 28 }
jb302@28 29 }
jb302@28 30
jb302@28 31 WIDE
jb302@28 32 get_wide(BYTE reg) {
jb302@29 33 /* high, low */
jb302@29 34 return MWIDE(regs[reg + 4], regs[reg + 12]);
jb302@28 35 }
jb302@28 36
jb302@28 37 void
jb302@28 38 set_wide(BYTE reg, WIDE val) {
jb302@29 39 regs[reg + 4] = GHIGH(val); /* high */
jb302@29 40 regs[reg + 12] = GLOW(val); /* low */
jb302@28 41 }
jb302@28 42
jb302@28 43 void
jb302@28 44 inc_pc(BYTE n) {
jb302@28 45 if ((regs[PCL] + n) > 0xFF) {
jb302@28 46 regs[PCH]++;
jb302@28 47 }
jb302@28 48 regs[PCL] += n;
jb302@28 49 }
jb302@28 50
jb302@28 51 BYTE
jb302@28 52 fetch(void) {
jb302@28 53 BYTE val = mem[get_wide(PC)];
jb302@28 54 inc_pc(1);
jb302@28 55 return val;
jb302@28 56 }
jb302@28 57
jb302@28 58 WIDE
jb302@28 59 fetch_wide(void) {
jb302@29 60 WIDE val = MWIDE(mem[get_wide(PC)], mem[get_wide(PC) + g1]);
jb302@28 61 inc_pc(2);
jb302@28 62 return val;
jb302@28 63 }
jb302@28 64
jb302@29 65 /* 0b000 = R0
jb302@29 66 * 0b001 = R1
jb302@29 67 * 0b010 = R2
jb302@29 68 * 0b011 = R3
jb302@29 69 * 0b100 = DPH
jb302@29 70 * 0b101 = DPL
jb302@29 71 * 0b110 = SPH
jb302@29 72 * 0b111 = SPL */
jb302@29 73 BYTE
jb302@29 74 get_reg(BYTE reg) {
jb302@29 75 if (reg < 4) {
jb302@29 76 return regs[reg | (get_flag(BS) << 3)];
jb302@29 77 }
jb302@29 78 else {
jb302@29 79 switch (reg) {
jb302@29 80
jb302@29 81 case 4:
jb302@29 82 return regs[DPH];
jb302@29 83 case 5:
jb302@29 84 return regs[DPL];
jb302@29 85 case 6:
jb302@29 86 return regs[SPH];
jb302@29 87 case 7:
jb302@29 88 return regs[SPL];
jb302@29 89 default:
jb302@29 90 return 0;
jb302@29 91 }
jb302@29 92 }
jb302@29 93 }
jb302@28 94
jb302@29 95 void
jb302@29 96 set_reg(BYTE reg, BYTE val) {
jb302@29 97 if (reg < 4) {
jb302@29 98 regs[reg | (get_flag(BS) << 3)] = val;
jb302@29 99 }
jb302@29 100 else {
jb302@29 101 switch (reg) {
jb302@29 102
jb302@29 103 case 4:
jb302@29 104 regs[DPH] = val;
jb302@29 105 break;
jb302@29 106 case 5:
jb302@29 107 regs[DPL] = val;
jb302@29 108 break;
jb302@29 109 case 6:
jb302@29 110 regs[SPH] = val;
jb302@29 111 break;
jb302@29 112 case 7:
jb302@29 113 regs[SPL] = val;
jb302@29 114 break;
jb302@29 115 default:
jb302@29 116 break;
jb302@29 117 }
jb302@29 118 }
jb302@29 119 }