changeset 40:419ce4ebfc4c staging

Further improvements in the PRU readibility (removed unnecssary defines and renamed r27_current back to reg_digital_current)

--- a/pru_rtaudio.p	Wed May 13 12:18:10 2015 +0100
+++ b/pru_rtaudio.p	Wed May 13 12:23:37 2015 +0100
@@ -189,7 +189,7 @@
 #define MEM_DIGITAL_BUFFER1_OFFSET 0x400 //Start pointer to DIGITAL_BUFFER1, which is 256 words after.
 // 256 is the maximum number of frames allowed
 
-#define r27_current r6  // Pointer to current storage location of DIGITAL
+#define reg_digital_current r6  // Pointer to current storage location of DIGITAL
 #define reg_num_channels	r9		// Number of SPI ADC/DAC channels to use
 #define reg_frame_current	r10		// Current frame count in SPI ADC/DAC transfer
 #define reg_frame_total		r11		// Total frame count for SPI ADC/DAC
@@ -211,7 +211,6 @@
 // r27, r28 used in macros
 #define reg_mcasp_addr		r29		// Base address for McASP
 
-// DIGITAL new code starts here
 //0  P8_07 36 0x890/090 66 gpio2[2]
 //1  P8_08 37 0x894/094 67 gpio2[3]
 //2  P8_09 39 0x89c/09c 69 gpio2[5]
@@ -229,8 +228,6 @@
 //14 P8_29 57 0x8e4/0e4 87 gpio2[23]
 //15 P8_30 59 0x8ec/0ec 89 gpio2[25]
 
-//TODO during initialization, set the pinmuxers to mode 7, input enable
- 
 //generic GPIOs constants
 //#define GPIO1 0x4804c000
 #define GPIO2 0x481ac000
@@ -238,18 +235,6 @@
 #define GPIO_OE 0x134 
 #define GPIO_DATAIN 0x138
 
-//gpioX_cleardataout must be adjacent to gpioX_setdataout
-#define reg_gpio1_oe r2
-#define reg_gpio2_oe r3
-#define reg_gpio2_cleardataout r4
-#define reg_gpio2_setdataout r5
-#define reg_gpio1_cleardataout r7
-#define reg_gpio1_setdataout r8
-#define reg_digital r27 //will first contain digitalOut from render() and digitalIn to render() later
-//aliases
-#define reg_gpio1_datain r2
-#define reg_gpio2_datain r3
-
 .macro READ_GPIO_BITS
 .mparam gpio_data, gpio_num_bit, digital_bit, digital
     QBBC DONE, digital, digital_bit //if the pin is set as an output, nothing to do here
@@ -500,11 +485,11 @@
 //- one taking place during DAC_WRITE which sets the GPIO_OE
 //- and the other during ADC_WRITE which actually reads DATAIN and writes CLEAR/SET DATAOUT
                             //r27 is actually r27, so do not use r27 from here to ...
-      LBBO r27, r27_current, 0, 4 
+      LBBO r27, reg_digital_current, 0, 4 
       JAL r28.w0, DIGITAL // note that this is not called as a macro, but with JAL. r28 will contain the return address
-      SBBO r27, r27_current, 0,   4 
+      SBBO r27, reg_digital_current, 0,   4 
                             //..here you can start using r27 again
-      ADD r27_current, r27_current, 4 //increment pointer
+      ADD reg_digital_current, reg_digital_current, 4 //increment pointer
 GPIO_DONE:
       ADC_WAIT_FOR_FINISH
       ADC_RX out
@@ -822,10 +807,10 @@
       MOV reg_frame_current, 0
       QBBS DIGITAL_BASE_CHECK_SET, reg_flags, FLAG_BIT_BUFFER1  //check which buffer we are using for DIGITAL
                   // if we are here, we are using buffer0 
-      MOV r27_current, MEM_DIGITAL_BASE
+      MOV reg_digital_current, MEM_DIGITAL_BASE
       QBA DIGITAL_BASE_CHECK_DONE
 DIGITAL_BASE_CHECK_SET: //if we are here, we are using buffer1 
-      MOV r27_current, MEM_DIGITAL_BASE+MEM_DIGITAL_BUFFER1_OFFSET //so adjust offset appropriately
+      MOV reg_digital_current, MEM_DIGITAL_BASE+MEM_DIGITAL_BUFFER1_OFFSET //so adjust offset appropriately
 DIGITAL_BASE_CHECK_DONE:
 
 WRITE_LOOP: