comparison pru_rtaudio.p @ 282:5b490c00488f prerelease

PRU update to support mux capelet

 #define COMM_FRAME_COUNT      32	  // How many frames have elapse since beginning
 #define COMM_USE_SPI          36          // Whether or not to use SPI ADC and DAC
 #define COMM_NUM_CHANNELS     40	  // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels
 #define COMM_USE_DIGITAL      44	  // Whether or not to use DIGITAL
 #define COMM_PRU_NUMBER       48          // Which PRU this code is running on
-
+#define COMM_MUX_CONFIG       52          // Whether to use the mux capelet, and how many channels
+
+// General constants for McASP peripherals (used for audio codec)
 #define MCASP0_BASE 0x48038000
 #define MCASP1_BASE 0x4803C000
 
 #define MCASP_PWRIDLESYSCONFIG 		0x04
 #define MCASP_PFUNC			0x10

 
 // Flags for the flags register
 #define FLAG_BIT_BUFFER1	0
 #define FLAG_BIT_USE_SPI	1
 #define FLAG_BIT_MCASP_HWORD	2		// Whether we are on the high word for McASP transmission
-#define FLAG_BIT_USE_DIGITAL 3
+#define FLAG_BIT_USE_DIGITAL	3
+	
+#define FLAG_BIT_MUX_CONFIG0	 8		// Mux capelet configuration:
+#define FLAG_BIT_MUX_CONFIG1	 9		// 00 = off, 01 = 2 ch., 10 = 4 ch., 11 = 8 ch.
+#define FLAG_MASK_MUX_CONFIG	 0x0300
+	
+#define FLAG_BIT_MUX_STATE0	10		// Current state of the mux channels
+#define FLAG_BIT_MUX_STATE1	11
+#define FLAG_BIT_MUX_STATE2	12
+#define FLAG_MASK_MUX_STATE	0x1C00
+	
 // Registers used throughout
 
 // r1, r2, r3 are used for temporary storage
 #define MEM_DIGITAL_BASE 0x11000 //Base address for DIGITAL : Shared RAM + 0x400
 #define MEM_DIGITAL_BUFFER1_OFFSET 0x400 //Start pointer to DIGITAL_BUFFER1, which is 256 words after.

 #define reg_flags		r24		// Buffer ID (0 and 1) and other flags
 #define reg_comm_addr		r25		// Memory address for communicating with ARM
 #define reg_spi_addr		r26		// Base address for SPI
 // r27, r28 used in macros
 #define reg_mcasp_addr		r29		// Base address for McASP
+#define reg_pru1_mux_pins	r30		// Register mapped directly to P8 pins (PRU1 only)
 
 //0  P8_07 36 0x890/090 66 gpio2[2]
 //1  P8_08 37 0x894/094 67 gpio2[3]
 //2  P8_09 39 0x89c/09c 69 gpio2[5]
 //3  P8_10 38 0x898/098 68 gpio2[4]

 POLL:
      LBBO r28, reg_mcasp_addr, reg, 4
      AND r28, r28, r27
      QBEQ POLL, r28, 0
 .endm
-   
+
+// Multiplexer Capelet: Increment channel on muxes 0-3
+.macro MUX_INCREMENT_0_TO_3
+     MOV r28, FLAG_MASK_MUX_CONFIG
+     AND r28, reg_flags, r28             // Check flags
+     QBEQ DONE, r28, 0                   // Skip if disabled
+     LSR r28, r28, FLAG_BIT_MUX_CONFIG0
+     AND r27, reg_pru1_mux_pins, 0x07    // Current mux channel in r30 bits 2-0
+     ADD r27, r27, 1            // Increment channel
+     AND r27, r27, 0x07         // Mask to 8 channels
+     QBEQ UPDATE, r28, 0x03
+     AND r27, r27, 0x03         // Mask to 4 channels
+     QBEQ UPDATE, r28, 0x02
+     AND r27, r27, 0x01         // Mask to 2 channels
+UPDATE:
+     MOV r28, 0xFFFFFFF8
+     AND r28, reg_pru1_mux_pins, r28  // Mask out low 3 bits of r30
+     OR  r28, r28, r27                // Combine with new value
+     MOV reg_pru1_mux_pins, r28       // Move back to r30 to propagate to pins
+DONE:
+.endm
+	
 START:
      // Load useful registers for addressing SPI
      MOV reg_comm_addr, SHARED_COMM_MEM_BASE
      MOV reg_spi_addr, SPI_BASE
      MOV reg_mcasp_addr, MCASP_BASE

      SBBO r2, r3, 0, 4 
      ADD r3, r3, 4 //increment pointer
      QBGT DIGITAL_INIT_BUFFER_LOOP, r3, r4 //loop until we reach the end of the buffer
 */
 DIGITAL_INIT_DONE:
+     // Check if we should use an external multiplexer capelet
+     // The valid values are 0 (off), 1 (2 ch), 2 (4 ch), 3 (8 ch)
+     // This can only happen on PRU1 because of how the pins are mapped
+     LBBO r2, reg_comm_addr, COMM_PRU_NUMBER, 4
+     QBNE MUX_INIT_DONE, r2, 1
+     LBBO r2, reg_comm_addr, COMM_MUX_CONFIG, 4
+     AND r2, r2, 0x03
+     QBEQ MUX_INIT_DONE, r2, 0
+     // If we get here, we are using the mux. Prepare flags and initial state.
+     LSL r2, r2, FLAG_BIT_MUX_CONFIG0
+     OR  reg_flags, reg_flags, r2
+     // Clear lower 6 bits of r30 which controls the mux pins
+     MOV r2, 0xFFFFFFC0
+     AND reg_pru1_mux_pins, reg_pru1_mux_pins, r2
+MUX_INIT_DONE:
+	
      // Find out whether we should use SPI ADC and DAC
      LBBO r2, reg_comm_addr, COMM_USE_SPI, 4
      QBEQ SPI_FLAG_CHECK_DONE, r2, 0
      SET reg_flags, reg_flags, FLAG_BIT_USE_SPI
 SPI_FLAG_CHECK_DONE:

 
      // Store 2 ADC words in memory
      SBCO reg_adc_data, C_ADC_DAC_MEM, reg_adc_current, 4
      ADD reg_adc_current, reg_adc_current, 4
 
+     // If enabled, update the multiplexer settings
+     QBNE MUX_0_3_DONE, r1, 3    // Change mux settings for ch0-3 after reading ch. 3
+     MUX_INCREMENT_0_TO_3
+MUX_0_3_DONE:
+	
      // Toggle the high/low word for McASP control (since we send one word out of
      // 32 bits for each pair of SPI channels)
      XOR reg_flags, reg_flags, (1 << FLAG_BIT_MCASP_HWORD)
 	
      // Repeat 4 times for 8 channels (2 samples per loop, r1 += 1 already happened)

      XOR reg_flags, reg_flags, (1 << FLAG_BIT_MCASP_HWORD)
 
      ADD r1, r1, 2
      QBNE ADC_DAC_LOOP, r1, reg_num_channels
 	
-ADC_DAC_LOOP_DONE:	
+ADC_DAC_LOOP_DONE:
      // Increment number of frames, see if we have more to write
      ADD reg_frame_current, reg_frame_current, 1
      QBNE WRITE_LOOP, reg_frame_current, reg_frame_total
 
 WRITE_LOOP_DONE: