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comparison src/fftw-3.3.8/dft/simd/common/t1sv_4.c @ 167:bd3cc4d1df30

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Add FFTW 3.3.8 source, and a Linux build
author Chris Cannam <cannam@all-day-breakfast.com>
date Tue, 19 Nov 2019 14:52:55 +0000
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166:cbd6d7e562c7 167:bd3cc4d1df30
1 /*
2 * Copyright (c) 2003, 2007-14 Matteo Frigo
3 * Copyright (c) 2003, 2007-14 Massachusetts Institute of Technology
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21 /* This file was automatically generated --- DO NOT EDIT */
22 /* Generated on Thu May 24 08:06:09 EDT 2018 */
23
24 #include "dft/codelet-dft.h"
25
26 #if defined(ARCH_PREFERS_FMA) || defined(ISA_EXTENSION_PREFERS_FMA)
27
28 /* Generated by: ../../../genfft/gen_twiddle.native -fma -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name t1sv_4 -include dft/simd/ts.h */
29
30 /*
31 * This function contains 22 FP additions, 12 FP multiplications,
32 * (or, 16 additions, 6 multiplications, 6 fused multiply/add),
33 * 15 stack variables, 0 constants, and 16 memory accesses
34 */
35 #include "dft/simd/ts.h"
36
37 static void t1sv_4(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
38 {
39 {
40 INT m;
41 for (m = mb, W = W + (mb * 6); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 6), MAKE_VOLATILE_STRIDE(8, rs)) {
42 V T1, Tv, T7, Tu, Te, To, Tk, Tq;
43 T1 = LD(&(ri[0]), ms, &(ri[0]));
44 Tv = LD(&(ii[0]), ms, &(ii[0]));
45 {
46 V T3, T6, T4, Tt, T2, T5;
47 T3 = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
48 T6 = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
49 T2 = LDW(&(W[TWVL * 2]));
50 T4 = VMUL(T2, T3);
51 Tt = VMUL(T2, T6);
52 T5 = LDW(&(W[TWVL * 3]));
53 T7 = VFMA(T5, T6, T4);
54 Tu = VFNMS(T5, T3, Tt);
55 }
56 {
57 V Ta, Td, Tb, Tn, T9, Tc;
58 Ta = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
59 Td = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
60 T9 = LDW(&(W[0]));
61 Tb = VMUL(T9, Ta);
62 Tn = VMUL(T9, Td);
63 Tc = LDW(&(W[TWVL * 1]));
64 Te = VFMA(Tc, Td, Tb);
65 To = VFNMS(Tc, Ta, Tn);
66 }
67 {
68 V Tg, Tj, Th, Tp, Tf, Ti;
69 Tg = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
70 Tj = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
71 Tf = LDW(&(W[TWVL * 4]));
72 Th = VMUL(Tf, Tg);
73 Tp = VMUL(Tf, Tj);
74 Ti = LDW(&(W[TWVL * 5]));
75 Tk = VFMA(Ti, Tj, Th);
76 Tq = VFNMS(Ti, Tg, Tp);
77 }
78 {
79 V T8, Tl, Ts, Tw;
80 T8 = VADD(T1, T7);
81 Tl = VADD(Te, Tk);
82 ST(&(ri[WS(rs, 2)]), VSUB(T8, Tl), ms, &(ri[0]));
83 ST(&(ri[0]), VADD(T8, Tl), ms, &(ri[0]));
84 Ts = VADD(To, Tq);
85 Tw = VADD(Tu, Tv);
86 ST(&(ii[0]), VADD(Ts, Tw), ms, &(ii[0]));
87 ST(&(ii[WS(rs, 2)]), VSUB(Tw, Ts), ms, &(ii[0]));
88 }
89 {
90 V Tm, Tr, Tx, Ty;
91 Tm = VSUB(T1, T7);
92 Tr = VSUB(To, Tq);
93 ST(&(ri[WS(rs, 3)]), VSUB(Tm, Tr), ms, &(ri[WS(rs, 1)]));
94 ST(&(ri[WS(rs, 1)]), VADD(Tm, Tr), ms, &(ri[WS(rs, 1)]));
95 Tx = VSUB(Tv, Tu);
96 Ty = VSUB(Te, Tk);
97 ST(&(ii[WS(rs, 1)]), VSUB(Tx, Ty), ms, &(ii[WS(rs, 1)]));
98 ST(&(ii[WS(rs, 3)]), VADD(Ty, Tx), ms, &(ii[WS(rs, 1)]));
99 }
100 }
101 }
102 VLEAVE();
103 }
104
105 static const tw_instr twinstr[] = {
106 VTW(0, 1),
107 VTW(0, 2),
108 VTW(0, 3),
109 {TW_NEXT, (2 * VL), 0}
110 };
111
112 static const ct_desc desc = { 4, XSIMD_STRING("t1sv_4"), twinstr, &GENUS, {16, 6, 6, 0}, 0, 0, 0 };
113
114 void XSIMD(codelet_t1sv_4) (planner *p) {
115 X(kdft_dit_register) (p, t1sv_4, &desc);
116 }
117 #else
118
119 /* Generated by: ../../../genfft/gen_twiddle.native -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name t1sv_4 -include dft/simd/ts.h */
120
121 /*
122 * This function contains 22 FP additions, 12 FP multiplications,
123 * (or, 16 additions, 6 multiplications, 6 fused multiply/add),
124 * 13 stack variables, 0 constants, and 16 memory accesses
125 */
126 #include "dft/simd/ts.h"
127
128 static void t1sv_4(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
129 {
130 {
131 INT m;
132 for (m = mb, W = W + (mb * 6); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 6), MAKE_VOLATILE_STRIDE(8, rs)) {
133 V T1, Tp, T6, To, Tc, Tk, Th, Tl;
134 T1 = LD(&(ri[0]), ms, &(ri[0]));
135 Tp = LD(&(ii[0]), ms, &(ii[0]));
136 {
137 V T3, T5, T2, T4;
138 T3 = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
139 T5 = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
140 T2 = LDW(&(W[TWVL * 2]));
141 T4 = LDW(&(W[TWVL * 3]));
142 T6 = VFMA(T2, T3, VMUL(T4, T5));
143 To = VFNMS(T4, T3, VMUL(T2, T5));
144 }
145 {
146 V T9, Tb, T8, Ta;
147 T9 = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
148 Tb = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
149 T8 = LDW(&(W[0]));
150 Ta = LDW(&(W[TWVL * 1]));
151 Tc = VFMA(T8, T9, VMUL(Ta, Tb));
152 Tk = VFNMS(Ta, T9, VMUL(T8, Tb));
153 }
154 {
155 V Te, Tg, Td, Tf;
156 Te = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
157 Tg = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
158 Td = LDW(&(W[TWVL * 4]));
159 Tf = LDW(&(W[TWVL * 5]));
160 Th = VFMA(Td, Te, VMUL(Tf, Tg));
161 Tl = VFNMS(Tf, Te, VMUL(Td, Tg));
162 }
163 {
164 V T7, Ti, Tn, Tq;
165 T7 = VADD(T1, T6);
166 Ti = VADD(Tc, Th);
167 ST(&(ri[WS(rs, 2)]), VSUB(T7, Ti), ms, &(ri[0]));
168 ST(&(ri[0]), VADD(T7, Ti), ms, &(ri[0]));
169 Tn = VADD(Tk, Tl);
170 Tq = VADD(To, Tp);
171 ST(&(ii[0]), VADD(Tn, Tq), ms, &(ii[0]));
172 ST(&(ii[WS(rs, 2)]), VSUB(Tq, Tn), ms, &(ii[0]));
173 }
174 {
175 V Tj, Tm, Tr, Ts;
176 Tj = VSUB(T1, T6);
177 Tm = VSUB(Tk, Tl);
178 ST(&(ri[WS(rs, 3)]), VSUB(Tj, Tm), ms, &(ri[WS(rs, 1)]));
179 ST(&(ri[WS(rs, 1)]), VADD(Tj, Tm), ms, &(ri[WS(rs, 1)]));
180 Tr = VSUB(Tp, To);
181 Ts = VSUB(Tc, Th);
182 ST(&(ii[WS(rs, 1)]), VSUB(Tr, Ts), ms, &(ii[WS(rs, 1)]));
183 ST(&(ii[WS(rs, 3)]), VADD(Ts, Tr), ms, &(ii[WS(rs, 1)]));
184 }
185 }
186 }
187 VLEAVE();
188 }
189
190 static const tw_instr twinstr[] = {
191 VTW(0, 1),
192 VTW(0, 2),
193 VTW(0, 3),
194 {TW_NEXT, (2 * VL), 0}
195 };
196
197 static const ct_desc desc = { 4, XSIMD_STRING("t1sv_4"), twinstr, &GENUS, {16, 6, 6, 0}, 0, 0, 0 };
198
199 void XSIMD(codelet_t1sv_4) (planner *p) {
200 X(kdft_dit_register) (p, t1sv_4, &desc);
201 }
202 #endif