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comparison src/fftw-3.3.3/dft/simd/common/t1sv_4.c @ 95:89f5e221ed7b

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Add FFTW3
author Chris Cannam <cannam@all-day-breakfast.com>
date Wed, 20 Mar 2013 15:35:50 +0000
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94:d278df1123f9 95:89f5e221ed7b
1 /*
2 * Copyright (c) 2003, 2007-11 Matteo Frigo
3 * Copyright (c) 2003, 2007-11 Massachusetts Institute of Technology
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21 /* This file was automatically generated --- DO NOT EDIT */
22 /* Generated on Sun Nov 25 07:39:24 EST 2012 */
23
24 #include "codelet-dft.h"
25
26 #ifdef HAVE_FMA
27
28 /* Generated by: ../../../genfft/gen_twiddle.native -fma -reorder-insns -schedule-for-pipeline -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name t1sv_4 -include ts.h */
29
30 /*
31 * This function contains 22 FP additions, 12 FP multiplications,
32 * (or, 16 additions, 6 multiplications, 6 fused multiply/add),
33 * 35 stack variables, 0 constants, and 16 memory accesses
34 */
35 #include "ts.h"
36
37 static void t1sv_4(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
38 {
39 {
40 INT m;
41 for (m = mb, W = W + (mb * 6); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 6), MAKE_VOLATILE_STRIDE(8, rs)) {
42 V T1, Tv, T3, T6, T5, Ta, Td, Tc, Tg, Tj, Tt, T4, Tf, Ti, Tn;
43 V Tb, T2, T9;
44 T1 = LD(&(ri[0]), ms, &(ri[0]));
45 Tv = LD(&(ii[0]), ms, &(ii[0]));
46 T3 = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
47 T6 = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
48 T2 = LDW(&(W[TWVL * 2]));
49 T5 = LDW(&(W[TWVL * 3]));
50 Ta = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
51 Td = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
52 T9 = LDW(&(W[0]));
53 Tc = LDW(&(W[TWVL * 1]));
54 Tg = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
55 Tj = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
56 Tt = VMUL(T2, T6);
57 T4 = VMUL(T2, T3);
58 Tf = LDW(&(W[TWVL * 4]));
59 Ti = LDW(&(W[TWVL * 5]));
60 Tn = VMUL(T9, Td);
61 Tb = VMUL(T9, Ta);
62 {
63 V Tu, T7, Tp, Th, To, Te;
64 Tu = VFNMS(T5, T3, Tt);
65 T7 = VFMA(T5, T6, T4);
66 Tp = VMUL(Tf, Tj);
67 Th = VMUL(Tf, Tg);
68 To = VFNMS(Tc, Ta, Tn);
69 Te = VFMA(Tc, Td, Tb);
70 {
71 V Tw, Tx, T8, Tm, Tq, Tk;
72 Tw = VADD(Tu, Tv);
73 Tx = VSUB(Tv, Tu);
74 T8 = VADD(T1, T7);
75 Tm = VSUB(T1, T7);
76 Tq = VFNMS(Ti, Tg, Tp);
77 Tk = VFMA(Ti, Tj, Th);
78 {
79 V Ts, Tr, Tl, Ty;
80 Ts = VADD(To, Tq);
81 Tr = VSUB(To, Tq);
82 Tl = VADD(Te, Tk);
83 Ty = VSUB(Te, Tk);
84 ST(&(ri[WS(rs, 1)]), VADD(Tm, Tr), ms, &(ri[WS(rs, 1)]));
85 ST(&(ri[WS(rs, 3)]), VSUB(Tm, Tr), ms, &(ri[WS(rs, 1)]));
86 ST(&(ii[WS(rs, 2)]), VSUB(Tw, Ts), ms, &(ii[0]));
87 ST(&(ii[0]), VADD(Ts, Tw), ms, &(ii[0]));
88 ST(&(ii[WS(rs, 3)]), VADD(Ty, Tx), ms, &(ii[WS(rs, 1)]));
89 ST(&(ii[WS(rs, 1)]), VSUB(Tx, Ty), ms, &(ii[WS(rs, 1)]));
90 ST(&(ri[0]), VADD(T8, Tl), ms, &(ri[0]));
91 ST(&(ri[WS(rs, 2)]), VSUB(T8, Tl), ms, &(ri[0]));
92 }
93 }
94 }
95 }
96 }
97 VLEAVE();
98 }
99
100 static const tw_instr twinstr[] = {
101 VTW(0, 1),
102 VTW(0, 2),
103 VTW(0, 3),
104 {TW_NEXT, (2 * VL), 0}
105 };
106
107 static const ct_desc desc = { 4, XSIMD_STRING("t1sv_4"), twinstr, &GENUS, {16, 6, 6, 0}, 0, 0, 0 };
108
109 void XSIMD(codelet_t1sv_4) (planner *p) {
110 X(kdft_dit_register) (p, t1sv_4, &desc);
111 }
112 #else /* HAVE_FMA */
113
114 /* Generated by: ../../../genfft/gen_twiddle.native -simd -compact -variables 4 -pipeline-latency 8 -n 4 -name t1sv_4 -include ts.h */
115
116 /*
117 * This function contains 22 FP additions, 12 FP multiplications,
118 * (or, 16 additions, 6 multiplications, 6 fused multiply/add),
119 * 13 stack variables, 0 constants, and 16 memory accesses
120 */
121 #include "ts.h"
122
123 static void t1sv_4(R *ri, R *ii, const R *W, stride rs, INT mb, INT me, INT ms)
124 {
125 {
126 INT m;
127 for (m = mb, W = W + (mb * 6); m < me; m = m + (2 * VL), ri = ri + ((2 * VL) * ms), ii = ii + ((2 * VL) * ms), W = W + ((2 * VL) * 6), MAKE_VOLATILE_STRIDE(8, rs)) {
128 V T1, Tp, T6, To, Tc, Tk, Th, Tl;
129 T1 = LD(&(ri[0]), ms, &(ri[0]));
130 Tp = LD(&(ii[0]), ms, &(ii[0]));
131 {
132 V T3, T5, T2, T4;
133 T3 = LD(&(ri[WS(rs, 2)]), ms, &(ri[0]));
134 T5 = LD(&(ii[WS(rs, 2)]), ms, &(ii[0]));
135 T2 = LDW(&(W[TWVL * 2]));
136 T4 = LDW(&(W[TWVL * 3]));
137 T6 = VFMA(T2, T3, VMUL(T4, T5));
138 To = VFNMS(T4, T3, VMUL(T2, T5));
139 }
140 {
141 V T9, Tb, T8, Ta;
142 T9 = LD(&(ri[WS(rs, 1)]), ms, &(ri[WS(rs, 1)]));
143 Tb = LD(&(ii[WS(rs, 1)]), ms, &(ii[WS(rs, 1)]));
144 T8 = LDW(&(W[0]));
145 Ta = LDW(&(W[TWVL * 1]));
146 Tc = VFMA(T8, T9, VMUL(Ta, Tb));
147 Tk = VFNMS(Ta, T9, VMUL(T8, Tb));
148 }
149 {
150 V Te, Tg, Td, Tf;
151 Te = LD(&(ri[WS(rs, 3)]), ms, &(ri[WS(rs, 1)]));
152 Tg = LD(&(ii[WS(rs, 3)]), ms, &(ii[WS(rs, 1)]));
153 Td = LDW(&(W[TWVL * 4]));
154 Tf = LDW(&(W[TWVL * 5]));
155 Th = VFMA(Td, Te, VMUL(Tf, Tg));
156 Tl = VFNMS(Tf, Te, VMUL(Td, Tg));
157 }
158 {
159 V T7, Ti, Tn, Tq;
160 T7 = VADD(T1, T6);
161 Ti = VADD(Tc, Th);
162 ST(&(ri[WS(rs, 2)]), VSUB(T7, Ti), ms, &(ri[0]));
163 ST(&(ri[0]), VADD(T7, Ti), ms, &(ri[0]));
164 Tn = VADD(Tk, Tl);
165 Tq = VADD(To, Tp);
166 ST(&(ii[0]), VADD(Tn, Tq), ms, &(ii[0]));
167 ST(&(ii[WS(rs, 2)]), VSUB(Tq, Tn), ms, &(ii[0]));
168 }
169 {
170 V Tj, Tm, Tr, Ts;
171 Tj = VSUB(T1, T6);
172 Tm = VSUB(Tk, Tl);
173 ST(&(ri[WS(rs, 3)]), VSUB(Tj, Tm), ms, &(ri[WS(rs, 1)]));
174 ST(&(ri[WS(rs, 1)]), VADD(Tj, Tm), ms, &(ri[WS(rs, 1)]));
175 Tr = VSUB(Tp, To);
176 Ts = VSUB(Tc, Th);
177 ST(&(ii[WS(rs, 1)]), VSUB(Tr, Ts), ms, &(ii[WS(rs, 1)]));
178 ST(&(ii[WS(rs, 3)]), VADD(Ts, Tr), ms, &(ii[WS(rs, 1)]));
179 }
180 }
181 }
182 VLEAVE();
183 }
184
185 static const tw_instr twinstr[] = {
186 VTW(0, 1),
187 VTW(0, 2),
188 VTW(0, 3),
189 {TW_NEXT, (2 * VL), 0}
190 };
191
192 static const ct_desc desc = { 4, XSIMD_STRING("t1sv_4"), twinstr, &GENUS, {16, 6, 6, 0}, 0, 0, 0 };
193
194 void XSIMD(codelet_t1sv_4) (planner *p) {
195 X(kdft_dit_register) (p, t1sv_4, &desc);
196 }
197 #endif /* HAVE_FMA */