jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: image/svg+xml jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: Internal control lines jb302@37: jb302@37: Address jb302@37: jb302@37: jb302@37: ALU jb302@37: TMP2 jb302@37: jb302@37: jb302@37: jb302@37: TMP1 jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: (TPL) (TPH) (TMPA) jb302@37: jb302@37: jb302@37: jb302@37: R0 R1 R2 (DPL) (DPH) jb302@37: R3 jb302@37: (SPL) (SPH) (PCL) (PCH) DPTR SP PC jb302@37: jb302@37: jb302@37: MAR jb302@37: jb302@37: 16 jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: MDR jb302@37: jb302@37: jb302@37: jb302@37: A jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: FLAGS jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: IR jb302@37: jb302@37: InstructionDecoder jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: Timing and Control M RD WR jb302@37: jb302@37: jb302@37: IO jb302@37: INT jb302@37: INTA jb302@37: jb302@37: Internal Data Bus jb302@37: jb302@37: jb302@37: 8 8 8 jb302@37: 8 jb302@37: jb302@37: 8-bit jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: Data Bus Address Bus jb302@37: jb302@37: 8 16 jb302@37: Main Memory64kB (65536 x 8-bit) RAM CE RD WR jb302@37: jb302@37: jb302@37: Data Address jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: I/O Port jb302@37: jb302@37: jb302@37: IN OUT CS RD WR jb302@37: jb302@37: Data jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: jb302@37: Interrupt EN jb302@37: jb302@37: jb302@37: jb302@37: port address decode logic jb302@37: jb302@37: LS8 addr jb302@37: jb302@37: