diff dbg/dbg.py @ 34:4411dee34085

cleaned out docs (don't worry they are comming back)
and added all my test files

--- a/dbg/dbg.py	Tue Apr 15 15:49:16 2014 +0100
+++ b/dbg/dbg.py	Wed Apr 16 16:51:39 2014 +0100
@@ -5,13 +5,17 @@
 from time import sleep
 
 # talks to the emulator
-# see dbgi() in emu/main.c for the inverse
+# see controller() in emu/main.c for the inverse
 class controller:
     
     def __init__(self):
         self.Emu = None
         open('out', 'w').close()
     
+    # Alternetive snd and rcv functions need to be
+    # written read/write using serial buffer to make
+    # this class talk to an emulator running on
+    # an MCU
     def snd(self, m):
         self.Emu.stdin.write(struct.pack('>B', m))
 
@@ -19,7 +23,7 @@
         lc = 0
         while lc != l:
             lc = os.path.getsize('out')
-        sleep(0.5)
+        #sleep(0.5)
         with open('out', 'r') as f:
             c = f.read()
         open('out', 'w').close()
@@ -28,10 +32,8 @@
     def step(self):
         self.snd(0x00)
 
-    def run(self, lenh, lenl):
+    def run(self):
         self.snd(0x01)
-        snd(lenh)
-        snd(lenl)
 
     def set_reg(self, reg, data):
         self.snd(0x02)
@@ -87,4 +89,21 @@
         self.snd(0x0B)
         return self.rcv(1)
 
+    def run_len(self, lenh, lenl):
+        self.snd(0x0C)
+        self.snd(lenh)
+        self.snd(lenl)
 
+    def free_run(self):
+        self.snd(0x0D)
+
+    def set_bp(self, i, addrh, addrl):
+        self.snd(0x0E)
+        self.snd(i)
+        self.snd(addrh)
+        self.snd(addrl)
+
+
+
+
+