changeset 253:33e0e4831763 prerelease

Started prerelease branch; updated PRU code to be able to run on either PRU.

--- a/core/PRU.cpp	Wed May 11 10:29:23 2016 +0100
+++ b/core/PRU.cpp	Mon May 16 12:13:58 2016 +0100
@@ -38,7 +38,7 @@
 using namespace std;
 
 #define PRU_MEM_MCASP_OFFSET 0x2000  // Offset within PRU-SHARED RAM
-#define PRU_MEM_MCASP_LENGTH 0x2000  // Length of McASP memory, in bytes
+#define PRU_MEM_MCASP_LENGTH 0x1000  // Length of McASP memory, in bytes
 #define PRU_MEM_DAC_OFFSET 0x0     // Offset within PRU0 RAM
 #define PRU_MEM_DAC_LENGTH 0x2000  // Length of ADC+DAC memory, in bytes
 #define PRU_MEM_COMM_OFFSET 0x0    // Offset within PRU-SHARED RAM
@@ -51,12 +51,13 @@
 #define PRU_SHOULD_SYNC     3
 #define PRU_SYNC_ADDRESS    4
 #define PRU_SYNC_PIN_MASK   5
-#define PRU_LED_ADDRESS		6
-#define PRU_LED_PIN_MASK	7
-#define PRU_FRAME_COUNT		8
-#define PRU_USE_SPI			9
+#define PRU_LED_ADDRESS	     6
+#define PRU_LED_PIN_MASK     7
+#define PRU_FRAME_COUNT      8
+#define PRU_USE_SPI          9
 #define PRU_SPI_NUM_CHANNELS 10
-#define PRU_USE_DIGITAL    11
+#define PRU_USE_DIGITAL      11
+#define PRU_PRU_NUMBER       12
 
 short int digitalPins[NUM_DIGITALS]={
 		GPIO_NO_BIT_0,
@@ -332,6 +333,7 @@
     pru_buffer_comm[PRU_SHOULD_SYNC] = 0;
     pru_buffer_comm[PRU_SYNC_ADDRESS] = 0;
     pru_buffer_comm[PRU_SYNC_PIN_MASK] = 0;
+    pru_buffer_comm[PRU_PRU_NUMBER] = pru_number;
     if(led_enabled) {
     	pru_buffer_comm[PRU_LED_ADDRESS] = USERLED3_GPIO_BASE;
     	pru_buffer_comm[PRU_LED_PIN_MASK] = USERLED3_PIN_MASK;

--- a/include/pru_rtaudio_bin.h	Wed May 11 10:29:23 2016 +0100
+++ b/include/pru_rtaudio_bin.h	Mon May 16 12:13:58 2016 +0100
@@ -275,20 +275,24 @@
      0xe1006287,
      0xe1006384,
      0x209c0000,
-     0x240002c3,
-     0x24202083,
-     0x240000e2,
-     0xe1002382,
-     0x240002c3,
-     0x24202883,
-     0x240120e2,
-     0xe1002382,
      0x240001d9,
      0x24000099,
      0x244803da,
      0x2401009a,
      0x244803dd,
      0x2480009d,
+     0x240002c0,
+     0x24400080,
+     0xf1303982,
+     0x5101e203,
+     0x240002c0,
+     0x24200080,
+     0x1320e0e3,
+     0x240000e2,
+     0xe1002382,
+     0x1328e0e3,
+     0x240120e2,
+     0xe1002382,
      0x91042480,
      0x1d04e0e0,
      0x81042480,
@@ -630,7 +634,7 @@
      0x79000002,
      0x0b10eee7,
      0xf1c03d82,
-     0xd500e29d,
+     0xd500e299,
      0xcf05e2fe,
      0x10e7e7fb,
      0x240208fc,
@@ -693,7 +697,7 @@
      0x4902e904,
      0x1101eafb,
      0x6900fb08,
-     0x2102b300,
+     0x2102b700,
      0x1103e1fb,
      0x6900fb05,
      0xf100269b,

--- a/pru_rtaudio.p	Wed May 11 10:29:23 2016 +0100
+++ b/pru_rtaudio.p	Mon May 16 12:13:58 2016 +0100
@@ -82,7 +82,8 @@
 #define COMM_FRAME_COUNT      32	  // How many frames have elapse since beginning
 #define COMM_USE_SPI          36          // Whether or not to use SPI ADC and DAC
 #define COMM_NUM_CHANNELS     40	  // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels
-#define COMM_USE_DIGITAL  44	  // Whether or not to use DIGITAL
+#define COMM_USE_DIGITAL      44	  // Whether or not to use DIGITAL
+#define COMM_PRU_NUMBER       48          // Which PRU this code is running on
 
 #define MCASP0_BASE 0x48038000
 #define MCASP1_BASE 0x4803C000
@@ -549,22 +550,30 @@
 .endm
    
 START:
+     // Load useful registers for addressing SPI
+     MOV reg_comm_addr, SHARED_COMM_MEM_BASE
+     MOV reg_spi_addr, SPI_BASE
+     MOV reg_mcasp_addr, MCASP_BASE
+
+     // Find out which PRU we are running on
+     // This affects the following offsets
+     MOV  r0, 0x24000      // PRU1 control register offset
+     LBBO r2, reg_comm_addr, COMM_PRU_NUMBER, 4
+     QBEQ PRU_NUMBER_CHECK_DONE, r2, 1
+     MOV  r0, 0x22000      // PRU0 control register offset
+PRU_NUMBER_CHECK_DONE:	
+	
      // Set up c24 and c25 offsets with CTBIR register
      // Thus C24 points to start of PRU0 RAM
-     MOV r3, 0x22020       // CTBIR0
+     OR  r3, r0, 0x20      // CTBIR0
      MOV r2, 0
      SBBO r2, r3, 0, 4
 
      // Set up c28 pointer offset for shared PRU RAM
-     MOV r3, 0x22028       // CTPPR0
+     OR r3, r0, 0x28       // CTPPR0
      MOV r2, 0x00000120    // To get address 0x00012000
      SBBO r2, r3, 0, 4
 	
-     // Load useful registers for addressing SPI
-     MOV reg_comm_addr, SHARED_COMM_MEM_BASE
-     MOV reg_spi_addr, SPI_BASE
-     MOV reg_mcasp_addr, MCASP_BASE
-	
      // Set ARM such that PRU can write to registers
      LBCO r0, C4, 4, 4
      CLR r0, r0, 4