# HG changeset patch
# User Giulio Moro <giuliomoro@yahoo.it>
# Date 1442278875 -3600
# Node ID e9a2f31dff7b71cb4a2c4821118338e7281e218b
# Parent  0a5a94de9dd0504e2341050ef4cfcc10b5bff796
Something weird happened when pllP=8, so I set pllP=7, which reduces (a bit) the clock adjustment precision

diff -r 0a5a94de9dd0 -r e9a2f31dff7b core/I2c_Codec.cpp
--- a/core/I2c_Codec.cpp	Mon Sep 14 21:39:54 2015 +0100
+++ b/core/I2c_Codec.cpp	Tue Sep 15 02:01:15 2015 +0100
@@ -47,9 +47,11 @@
 	// The master clock PLLCLK_IN is 12MHz
 	// K can be varied in intervals of resolution of 0.0001 up to 63.9999
 	// using P=8 and R=1 gives a resolution of 0.0732421875Hz ( 0.000166% at 44.1kHz)
+	// for whatever reason, P=8 does not work (i.e.: setting the sampling rate works fine,
+	// but when changing K by a small-ish value (0.0040), the clock does not seem to change).
 	// to obtain Fs=44100 we need to have K=60.2112
 
-	if(setPllP(8))
+	if(setPllP(7))
 		return 1;
 	if(setPllR(1))
 		return 1;
@@ -217,7 +219,9 @@
 	long int PLLCLK_IN=12000000;
 	//	f_{S(ref)} = (PLLCLK_IN × K × R)/(2048 × P)
 	float k = ((double)(newSamplingRate * pllP * 2048.0f/(float)pllR)) / PLLCLK_IN ;
-	return (setPllK(k));
+	int ret = setPllK(k);
+//	printf("P: %d, R: %d, J: %d, D: %d\n", pllP, pllR, pllJ, pllD);
+	return ret;
 }
 
 short unsigned int I2c_Codec::getPllJ(){