andrewm@0: .origin 0 andrewm@0: .entrypoint START andrewm@0: andrewm@0: #define DBOX_CAPE // Define this to use new cape hardware andrewm@0: andrewm@0: #define CLOCK_BASE 0x44E00000 andrewm@0: #define CLOCK_SPI0 0x4C andrewm@0: #define CLOCK_SPI1 0x50 andrewm@0: #define CLOCK_L4LS 0x60 andrewm@0: andrewm@0: #define SPI0_BASE 0x48030100 andrewm@0: #define SPI1_BASE 0x481A0100 andrewm@0: #define SPI_BASE SPI0_BASE andrewm@0: andrewm@0: #define SPI_SYSCONFIG 0x10 andrewm@0: #define SPI_SYSSTATUS 0x14 andrewm@0: #define SPI_MODULCTRL 0x28 andrewm@0: #define SPI_CH0CONF 0x2C andrewm@0: #define SPI_CH0STAT 0x30 andrewm@0: #define SPI_CH0CTRL 0x34 andrewm@0: #define SPI_CH0TX 0x38 andrewm@0: #define SPI_CH0RX 0x3C andrewm@0: #define SPI_CH1CONF 0x40 andrewm@0: #define SPI_CH1STAT 0x44 andrewm@0: #define SPI_CH1CTRL 0x48 andrewm@0: #define SPI_CH1TX 0x4C andrewm@0: #define SPI_CH1RX 0x50 andrewm@0: andrewm@0: #define GPIO0 0x44E07000 andrewm@0: #define GPIO1 0x4804C000 andrewm@0: #define GPIO_CLEARDATAOUT 0x190 andrewm@0: #define GPIO_SETDATAOUT 0x194 andrewm@0: andrewm@0: #define PRU0_ARM_INTERRUPT 19 andrewm@0: andrewm@0: #define C_ADC_DAC_MEM C24 // PRU0 mem andrewm@0: #ifdef DBOX_CAPE andrewm@0: #define DAC_GPIO GPIO0 andrewm@0: #define DAC_CS_PIN (1<<5) // GPIO0:5 = P9 pin 17 andrewm@0: #else andrewm@0: #define DAC_GPIO GPIO1 andrewm@0: #define DAC_CS_PIN (1<<16) // GPIO1:16 = P9 pin 15 andrewm@0: #endif andrewm@0: #define DAC_TRM 0 // SPI transmit and receive andrewm@0: #define DAC_WL 32 // Word length andrewm@0: #define DAC_CLK_MODE 1 // SPI mode andrewm@0: #define DAC_CLK_DIV 1 // Clock divider (48MHz / 2^n) andrewm@0: #define DAC_DPE 1 // d0 = receive, d1 = transmit andrewm@0: andrewm@0: #define AD5668_COMMAND_OFFSET 24 andrewm@0: #define AD5668_ADDRESS_OFFSET 20 andrewm@0: #define AD5668_DATA_OFFSET 4 andrewm@0: #define AD5668_REF_OFFSET 0 andrewm@0: andrewm@0: #ifdef DBOX_CAPE andrewm@0: #define ADC_GPIO GPIO1 andrewm@0: #define ADC_CS_PIN (1<<16) // GPIO1:16 = P9 pin 15 andrewm@0: #else andrewm@0: #define ADC_GPIO GPIO1 andrewm@0: #define ADC_CS_PIN (1<<17) // GPIO1:17 = P9 pin 23 andrewm@0: #endif andrewm@0: #define ADC_TRM 0 // SPI transmit and receive andrewm@0: #define ADC_WL 16 // Word length andrewm@0: #define ADC_CLK_MODE 0 // SPI mode andrewm@0: #define ADC_CLK_DIV 1 // Clock divider (48MHz / 2^n) andrewm@0: #define ADC_DPE 1 // d0 = receive, d1 = transmit andrewm@0: andrewm@0: #define AD7699_CFG_MASK 0xF120 // Mask for config update, unipolar, full BW andrewm@0: #define AD7699_CHANNEL_OFFSET 9 // 7 bits offset of a 14-bit left-justified word andrewm@0: #define AD7699_SEQ_OFFSET 3 // sequencer (0 = disable, 3 = scan all) andrewm@0: andrewm@0: #define SHARED_COMM_MEM_BASE 0x00010000 // Location where comm flags are written andrewm@0: #define COMM_SHOULD_STOP 0 // Set to be nonzero when loop should stop andrewm@0: #define COMM_CURRENT_BUFFER 4 // Which buffer we are on andrewm@0: #define COMM_BUFFER_FRAMES 8 // How many frames per buffer andrewm@0: #define COMM_SHOULD_SYNC 12 // Whether to synchronise to an external clock andrewm@0: #define COMM_SYNC_ADDRESS 16 // Which memory address to find the GPIO on andrewm@0: #define COMM_SYNC_PIN_MASK 20 // Which pin to read for the sync andrewm@0: #define COMM_LED_ADDRESS 24 // Which memory address to find the status LED on andrewm@0: #define COMM_LED_PIN_MASK 28 // Which pin to write to change LED andrewm@0: #define COMM_FRAME_COUNT 32 // How many frames have elapse since beginning andrewm@0: #define COMM_USE_SPI 36 // Whether or not to use SPI ADC and DAC andrewm@12: #define COMM_NUM_CHANNELS 40 // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels andrewm@0: andrewm@0: #define MCASP0_BASE 0x48038000 andrewm@0: #define MCASP1_BASE 0x4803C000 andrewm@0: andrewm@0: #define MCASP_PWRIDLESYSCONFIG 0x04 andrewm@0: #define MCASP_PFUNC 0x10 andrewm@0: #define MCASP_PDIR 0x14 andrewm@0: #define MCASP_PDOUT 0x18 andrewm@0: #define MCASP_PDSET 0x1C andrewm@0: #define MCASP_PDIN 0x1C andrewm@0: #define MCASP_PDCLR 0x20 andrewm@0: #define MCASP_GBLCTL 0x44 andrewm@0: #define MCASP_AMUTE 0x48 andrewm@0: #define MCASP_DLBCTL 0x4C andrewm@0: #define MCASP_DITCTL 0x50 andrewm@0: #define MCASP_RGBLCTL 0x60 andrewm@0: #define MCASP_RMASK 0x64 andrewm@0: #define MCASP_RFMT 0x68 andrewm@0: #define MCASP_AFSRCTL 0x6C andrewm@0: #define MCASP_ACLKRCTL 0x70 andrewm@0: #define MCASP_AHCLKRCTL 0x74 andrewm@0: #define MCASP_RTDM 0x78 andrewm@0: #define MCASP_RINTCTL 0x7C andrewm@0: #define MCASP_RSTAT 0x80 andrewm@0: #define MCASP_RSLOT 0x84 andrewm@0: #define MCASP_RCLKCHK 0x88 andrewm@0: #define MCASP_REVTCTL 0x8C andrewm@0: #define MCASP_XGBLCTL 0xA0 andrewm@0: #define MCASP_XMASK 0xA4 andrewm@0: #define MCASP_XFMT 0xA8 andrewm@0: #define MCASP_AFSXCTL 0xAC andrewm@0: #define MCASP_ACLKXCTL 0xB0 andrewm@0: #define MCASP_AHCLKXCTL 0xB4 andrewm@0: #define MCASP_XTDM 0xB8 andrewm@0: #define MCASP_XINTCTL 0xBC andrewm@0: #define MCASP_XSTAT 0xC0 andrewm@0: #define MCASP_XSLOT 0xC4 andrewm@0: #define MCASP_XCLKCHK 0xC8 andrewm@0: #define MCASP_XEVTCTL 0xCC andrewm@0: #define MCASP_SRCTL0 0x180 andrewm@0: #define MCASP_SRCTL1 0x184 andrewm@0: #define MCASP_SRCTL2 0x188 andrewm@0: #define MCASP_SRCTL3 0x18C andrewm@0: #define MCASP_SRCTL4 0x190 andrewm@0: #define MCASP_SRCTL5 0x194 andrewm@0: #define MCASP_XBUF0 0x200 andrewm@0: #define MCASP_XBUF1 0x204 andrewm@0: #define MCASP_XBUF2 0x208 andrewm@0: #define MCASP_XBUF3 0x20C andrewm@0: #define MCASP_XBUF4 0x210 andrewm@0: #define MCASP_XBUF5 0x214 andrewm@0: #define MCASP_RBUF0 0x280 andrewm@0: #define MCASP_RBUF1 0x284 andrewm@0: #define MCASP_RBUF2 0x288 andrewm@0: #define MCASP_RBUF3 0x28C andrewm@0: #define MCASP_RBUF4 0x290 andrewm@0: #define MCASP_RBUF5 0x294 andrewm@0: #define MCASP_WFIFOCTL 0x1000 andrewm@0: #define MCASP_WFIFOSTS 0x1004 andrewm@0: #define MCASP_RFIFOCTL 0x1008 andrewm@0: #define MCASP_RFIFOSTS 0x100C andrewm@0: andrewm@0: #define MCASP_XSTAT_XDATA_BIT 5 // Bit to test for transmit ready andrewm@0: #define MCASP_RSTAT_RDATA_BIT 5 // Bit to test for receive ready andrewm@0: andrewm@0: // Constants used for this particular audio setup andrewm@0: #define MCASP_BASE MCASP0_BASE andrewm@0: #ifdef DBOX_CAPE andrewm@0: #define MCASP_SRCTL_X MCASP_SRCTL2 // Ser. 2 is transmitter andrewm@0: #define MCASP_SRCTL_R MCASP_SRCTL0 // Ser. 0 is receiver andrewm@0: #define MCASP_XBUF MCASP_XBUF2 andrewm@0: #define MCASP_RBUF MCASP_RBUF0 andrewm@0: #else andrewm@0: #define MCASP_SRCTL_X MCASP_SRCTL3 // Ser. 3 is transmitter andrewm@0: #define MCASP_SRCTL_R MCASP_SRCTL2 // Ser. 2 is receiver andrewm@0: #define MCASP_XBUF MCASP_XBUF3 andrewm@0: #define MCASP_RBUF MCASP_RBUF2 andrewm@0: #endif andrewm@0: andrewm@0: #define MCASP_PIN_AFSX (1 << 28) andrewm@0: #define MCASP_PIN_AHCLKX (1 << 27) andrewm@0: #define MCASP_PIN_ACLKX (1 << 26) andrewm@0: #define MCASP_PIN_AMUTE (1 << 25) // Also, 0 to 3 are XFR0 to XFR3 andrewm@0: andrewm@0: #ifdef DBOX_CAPE andrewm@0: #define MCASP_OUTPUT_PINS MCASP_PIN_AHCLKX | (1 << 2) // AHCLKX and AXR2 outputs andrewm@0: #else andrewm@0: #define MCASP_OUTPUT_PINS (1 << 3) // Which pins are outputs andrewm@0: #endif andrewm@0: andrewm@0: #define MCASP_DATA_MASK 0xFFFF // 16 bit data andrewm@0: #define MCASP_DATA_FORMAT 0x807C // MSB first, 0 bit delay, 16 bits, CFG bus, ROR 16bits andrewm@0: andrewm@12: #define C_MCASP_MEM C28 // Shared PRU mem andrewm@0: andrewm@0: // Flags for the flags register andrewm@0: #define FLAG_BIT_BUFFER1 0 andrewm@0: #define FLAG_BIT_USE_SPI 1 andrewm@12: #define FLAG_BIT_MCASP_HWORD 2 // Whether we are on the high word for McASP transmission andrewm@0: andrewm@0: // Registers used throughout andrewm@0: andrewm@0: // r1, r2, r3 are used for temporary storage andrewm@12: #define reg_num_channels r9 // Number of SPI ADC/DAC channels to use andrewm@0: #define reg_frame_current r10 // Current frame count in SPI ADC/DAC transfer andrewm@0: #define reg_frame_total r11 // Total frame count for SPI ADC/DAC andrewm@0: #define reg_dac_data r12 // Current dword for SPI DAC andrewm@0: #define reg_adc_data r13 // Current dword for SPI ADC andrewm@0: #define reg_mcasp_dac_data r14 // Current dword for McASP DAC andrewm@0: #define reg_mcasp_adc_data r15 // Current dword for McASP ADC andrewm@0: #define reg_dac_buf0 r16 // Start pointer to SPI DAC buffer 0 andrewm@0: #define reg_dac_buf1 r17 // Start pointer to SPI DAC buffer 1 andrewm@0: #define reg_dac_current r18 // Pointer to current storage location of SPI DAC andrewm@0: #define reg_adc_current r19 // Pointer to current storage location of SPI ADC andrewm@0: #define reg_mcasp_buf0 r20 // Start pointer to McASP DAC buffer 0 andrewm@0: #define reg_mcasp_buf1 r21 // Start pointer to McASP DAC buffer 1 andrewm@0: #define reg_mcasp_dac_current r22 // Pointer to current storage location of McASP DAC andrewm@0: #define reg_mcasp_adc_current r23 // Pointer to current storage location of McASP ADC andrewm@0: #define reg_flags r24 // Buffer ID (0 and 1) and other flags andrewm@0: #define reg_comm_addr r25 // Memory address for communicating with ARM andrewm@0: #define reg_spi_addr r26 // Base address for SPI andrewm@0: // r27, r28 used in macros andrewm@0: #define reg_mcasp_addr r29 // Base address for McASP andrewm@0: andrewm@0: andrewm@0: // Bring CS line low to write to DAC andrewm@0: .macro DAC_CS_ASSERT andrewm@0: MOV r27, DAC_CS_PIN andrewm@0: MOV r28, DAC_GPIO + GPIO_CLEARDATAOUT andrewm@0: SBBO r27, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Bring CS line high at end of DAC transaction andrewm@0: .macro DAC_CS_UNASSERT andrewm@0: MOV r27, DAC_CS_PIN andrewm@0: MOV r28, DAC_GPIO + GPIO_SETDATAOUT andrewm@0: SBBO r27, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Write to DAC TX register andrewm@0: .macro DAC_TX andrewm@0: .mparam data andrewm@0: SBBO data, reg_spi_addr, SPI_CH0TX, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Wait for SPI to finish (uses RXS indicator) andrewm@0: .macro DAC_WAIT_FOR_FINISH andrewm@0: LOOP: andrewm@0: LBBO r27, reg_spi_addr, SPI_CH0STAT, 4 andrewm@0: QBBC LOOP, r27, 0 andrewm@0: .endm andrewm@0: andrewm@0: // Read the RX word to clear andrewm@0: .macro DAC_DISCARD_RX andrewm@0: LBBO r27, reg_spi_addr, SPI_CH0RX, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Complete DAC write with chip select andrewm@0: .macro DAC_WRITE andrewm@0: .mparam reg andrewm@0: DAC_CS_ASSERT andrewm@0: DAC_TX reg andrewm@0: DAC_WAIT_FOR_FINISH andrewm@0: DAC_CS_UNASSERT andrewm@0: DAC_DISCARD_RX andrewm@0: .endm andrewm@0: andrewm@0: // Bring CS line low to write to ADC andrewm@0: .macro ADC_CS_ASSERT andrewm@0: MOV r27, ADC_CS_PIN andrewm@0: MOV r28, ADC_GPIO + GPIO_CLEARDATAOUT andrewm@0: SBBO r27, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Bring CS line high at end of ADC transaction andrewm@0: .macro ADC_CS_UNASSERT andrewm@0: MOV r27, ADC_CS_PIN andrewm@0: MOV r28, ADC_GPIO + GPIO_SETDATAOUT andrewm@0: SBBO r27, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Write to ADC TX register andrewm@0: .macro ADC_TX andrewm@0: .mparam data andrewm@0: SBBO data, reg_spi_addr, SPI_CH1TX, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Wait for SPI to finish (uses RXS indicator) andrewm@0: .macro ADC_WAIT_FOR_FINISH andrewm@0: LOOP: andrewm@0: LBBO r27, reg_spi_addr, SPI_CH1STAT, 4 andrewm@0: QBBC LOOP, r27, 0 andrewm@0: .endm andrewm@0: andrewm@0: // Read the RX word to clear; store output andrewm@0: .macro ADC_RX andrewm@0: .mparam data andrewm@0: LBBO data, reg_spi_addr, SPI_CH1RX, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Complete ADC write+read with chip select andrewm@0: .macro ADC_WRITE andrewm@0: .mparam in, out andrewm@0: ADC_CS_ASSERT andrewm@0: ADC_TX in andrewm@0: ADC_WAIT_FOR_FINISH andrewm@0: ADC_RX out andrewm@0: ADC_CS_UNASSERT andrewm@0: .endm andrewm@0: andrewm@0: // Write a McASP register andrewm@0: .macro MCASP_REG_WRITE andrewm@0: .mparam reg, value andrewm@0: MOV r27, value andrewm@0: SBBO r27, reg_mcasp_addr, reg, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Write a McASP register beyond the 0xFF boundary andrewm@0: .macro MCASP_REG_WRITE_EXT andrewm@0: .mparam reg, value andrewm@0: MOV r27, value andrewm@0: MOV r28, reg andrewm@0: ADD r28, reg_mcasp_addr, r28 andrewm@0: SBBO r27, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Read a McASP register andrewm@0: .macro MCASP_REG_READ andrewm@0: .mparam reg, value andrewm@0: LBBO value, reg_mcasp_addr, reg, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Read a McASP register beyond the 0xFF boundary andrewm@0: .macro MCASP_REG_READ_EXT andrewm@0: .mparam reg, value andrewm@0: MOV r28, reg andrewm@0: ADD r28, reg_mcasp_addr, r28 andrewm@0: LBBO value, r28, 0, 4 andrewm@0: .endm andrewm@0: andrewm@0: // Set a bit and wait for it to come up andrewm@0: .macro MCASP_REG_SET_BIT_AND_POLL andrewm@0: .mparam reg, mask andrewm@0: MOV r27, mask andrewm@0: LBBO r28, reg_mcasp_addr, reg, 4 andrewm@0: OR r28, r28, r27 andrewm@0: SBBO r28, reg_mcasp_addr, reg, 4 andrewm@0: POLL: andrewm@0: LBBO r28, reg_mcasp_addr, reg, 4 andrewm@0: AND r28, r28, r27 andrewm@0: QBEQ POLL, r28, 0 andrewm@0: .endm andrewm@0: andrewm@0: START: andrewm@0: // Set up c24 and c25 offsets with CTBIR register andrewm@0: // Thus C24 points to start of PRU0 RAM andrewm@0: MOV r3, 0x22020 // CTBIR0 andrewm@0: MOV r2, 0 andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: // Set up c28 pointer offset for shared PRU RAM andrewm@0: MOV r3, 0x22028 // CTPPR0 andrewm@0: MOV r2, 0x00000120 // To get address 0x00012000 andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: // Load useful registers for addressing SPI andrewm@0: MOV reg_comm_addr, SHARED_COMM_MEM_BASE andrewm@0: MOV reg_spi_addr, SPI_BASE andrewm@0: MOV reg_mcasp_addr, MCASP_BASE andrewm@0: andrewm@0: // Set ARM such that PRU can write to registers andrewm@0: LBCO r0, C4, 4, 4 andrewm@0: CLR r0, r0, 4 andrewm@0: SBCO r0, C4, 4, 4 andrewm@0: andrewm@0: // Clear flags andrewm@0: MOV reg_flags, 0 andrewm@0: andrewm@12: // Default number of channels in case SPI disabled andrewm@12: LDI reg_num_channels, 8 andrewm@12: andrewm@0: // Find out whether we should use SPI ADC and DAC andrewm@0: LBBO r2, reg_comm_addr, COMM_USE_SPI, 4 andrewm@0: QBEQ SPI_FLAG_CHECK_DONE, r2, 0 andrewm@0: SET reg_flags, reg_flags, FLAG_BIT_USE_SPI andrewm@0: andrewm@0: SPI_FLAG_CHECK_DONE: andrewm@0: // If we don't use SPI, then skip all this init andrewm@0: QBBC SPI_INIT_DONE, reg_flags, FLAG_BIT_USE_SPI andrewm@12: andrewm@12: // Load the number of channels: valid values are 8, 4 or 2 andrewm@12: LBBO reg_num_channels, reg_comm_addr, COMM_NUM_CHANNELS, 4 andrewm@12: QBGT SPI_NUM_CHANNELS_LT8, reg_num_channels, 8 // 8 > num_channels ? andrewm@12: LDI reg_num_channels, 8 // If N >= 8, N = 8 andrewm@12: QBA SPI_NUM_CHANNELS_DONE andrewm@12: SPI_NUM_CHANNELS_LT8: andrewm@12: QBGT SPI_NUM_CHANNELS_LT4, reg_num_channels, 4 // 4 > num_channels ? andrewm@12: LDI reg_num_channels, 4 // If N >= 4, N = 4 andrewm@12: QBA SPI_NUM_CHANNELS_DONE andrewm@12: SPI_NUM_CHANNELS_LT4: andrewm@12: LDI reg_num_channels, 2 // else N = 2 andrewm@12: SPI_NUM_CHANNELS_DONE: andrewm@0: andrewm@0: // Init SPI clock andrewm@0: MOV r2, 0x02 andrewm@0: MOV r3, CLOCK_BASE + CLOCK_SPI0 andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: // Reset SPI and wait for finish andrewm@0: MOV r2, 0x02 andrewm@0: SBBO r2, reg_spi_addr, SPI_SYSCONFIG, 4 andrewm@0: andrewm@0: SPI_WAIT_RESET: andrewm@0: LBBO r2, reg_spi_addr, SPI_SYSSTATUS, 4 andrewm@0: QBBC SPI_WAIT_RESET, r2, 0 andrewm@0: andrewm@0: // Turn off SPI channels andrewm@0: MOV r2, 0 andrewm@0: SBBO r2, reg_spi_addr, SPI_CH0CTRL, 4 andrewm@0: SBBO r2, reg_spi_addr, SPI_CH1CTRL, 4 andrewm@0: andrewm@0: // Set to master; chip select lines enabled (CS0 used for DAC) andrewm@0: MOV r2, 0x00 andrewm@0: SBBO r2, reg_spi_addr, SPI_MODULCTRL, 4 andrewm@0: andrewm@0: // Configure CH0 for DAC andrewm@0: MOV r2, (3 << 27) | (DAC_DPE << 16) | (DAC_TRM << 12) | ((DAC_WL - 1) << 7) | (DAC_CLK_DIV << 2) | DAC_CLK_MODE | (1 << 6) andrewm@0: SBBO r2, reg_spi_addr, SPI_CH0CONF, 4 andrewm@0: andrewm@0: // Configure CH1 for ADC andrewm@0: MOV r2, (3 << 27) | (ADC_DPE << 16) | (ADC_TRM << 12) | ((ADC_WL - 1) << 7) | (ADC_CLK_DIV << 2) | ADC_CLK_MODE andrewm@0: SBBO r2, reg_spi_addr, SPI_CH1CONF, 4 andrewm@0: andrewm@0: // Turn on SPI channels andrewm@0: MOV r2, 0x01 andrewm@0: SBBO r2, reg_spi_addr, SPI_CH0CTRL, 4 andrewm@0: SBBO r2, reg_spi_addr, SPI_CH1CTRL, 4 andrewm@0: andrewm@0: // DAC power-on reset sequence andrewm@0: MOV r2, (0x07 << AD5668_COMMAND_OFFSET) andrewm@0: DAC_WRITE r2 andrewm@0: andrewm@0: // Initialise ADC andrewm@0: MOV r2, AD7699_CFG_MASK | (0 << AD7699_CHANNEL_OFFSET) | (0 << AD7699_SEQ_OFFSET) andrewm@0: ADC_WRITE r2, r2 andrewm@0: andrewm@0: // Enable DAC internal reference andrewm@0: MOV r2, (0x08 << AD5668_COMMAND_OFFSET) | (0x01 << AD5668_REF_OFFSET) andrewm@0: DAC_WRITE r2 andrewm@0: andrewm@0: // Read ADC ch0 and ch1: result is always 2 samples behind so start here andrewm@0: MOV r2, AD7699_CFG_MASK | (0x00 << AD7699_CHANNEL_OFFSET) andrewm@0: ADC_WRITE r2, r2 andrewm@0: andrewm@0: MOV r2, AD7699_CFG_MASK | (0x01 << AD7699_CHANNEL_OFFSET) andrewm@0: ADC_WRITE r2, r2 andrewm@0: SPI_INIT_DONE: andrewm@0: andrewm@0: // Prepare McASP0 for audio andrewm@0: MCASP_REG_WRITE MCASP_GBLCTL, 0 // Disable McASP andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL0, 0 // All serialisers off andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL1, 0 andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL2, 0 andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL3, 0 andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL4, 0 andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL5, 0 andrewm@0: andrewm@0: MCASP_REG_WRITE MCASP_PWRIDLESYSCONFIG, 0x02 // Power on andrewm@0: MCASP_REG_WRITE MCASP_PFUNC, 0x00 // All pins are McASP andrewm@0: MCASP_REG_WRITE MCASP_PDIR, MCASP_OUTPUT_PINS // Set pin direction andrewm@0: MCASP_REG_WRITE MCASP_DLBCTL, 0x00 andrewm@0: MCASP_REG_WRITE MCASP_DITCTL, 0x00 andrewm@0: MCASP_REG_WRITE MCASP_RMASK, MCASP_DATA_MASK // 16 bit data receive andrewm@0: MCASP_REG_WRITE MCASP_RFMT, MCASP_DATA_FORMAT // Set data format andrewm@0: MCASP_REG_WRITE MCASP_AFSRCTL, 0x100 // I2S mode andrewm@0: MCASP_REG_WRITE MCASP_ACLKRCTL, 0x80 // Sample on rising edge andrewm@0: MCASP_REG_WRITE MCASP_AHCLKRCTL, 0x8001 // Internal clock, not inv, /2; irrelevant? andrewm@0: MCASP_REG_WRITE MCASP_RTDM, 0x03 // Enable TDM slots 0 and 1 andrewm@0: MCASP_REG_WRITE MCASP_RINTCTL, 0x00 // No interrupts andrewm@0: MCASP_REG_WRITE MCASP_XMASK, MCASP_DATA_MASK // 16 bit data transmit andrewm@0: MCASP_REG_WRITE MCASP_XFMT, MCASP_DATA_FORMAT // Set data format andrewm@0: MCASP_REG_WRITE MCASP_AFSXCTL, 0x100 // I2S mode andrewm@0: MCASP_REG_WRITE MCASP_ACLKXCTL, 0x00 // Transmit on rising edge, sync. xmit and recv andrewm@0: MCASP_REG_WRITE MCASP_AHCLKXCTL, 0x8001 // External clock from AHCLKX andrewm@0: MCASP_REG_WRITE MCASP_XTDM, 0x03 // Enable TDM slots 0 and 1 andrewm@0: MCASP_REG_WRITE MCASP_XINTCTL, 0x00 // No interrupts andrewm@0: andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL_R, 0x02 // Set up receive serialiser andrewm@0: MCASP_REG_WRITE_EXT MCASP_SRCTL_X, 0x01 // Set up transmit serialiser andrewm@0: MCASP_REG_WRITE_EXT MCASP_WFIFOCTL, 0x00 // Disable FIFOs andrewm@0: MCASP_REG_WRITE_EXT MCASP_RFIFOCTL, 0x00 andrewm@0: andrewm@0: MCASP_REG_WRITE MCASP_XSTAT, 0xFF // Clear transmit errors andrewm@0: MCASP_REG_WRITE MCASP_RSTAT, 0xFF // Clear receive errors andrewm@0: andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_RGBLCTL, (1 << 1) // Set RHCLKRST andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_XGBLCTL, (1 << 9) // Set XHCLKRST andrewm@0: andrewm@0: // The above write sequence will have temporarily changed the AHCLKX frequency andrewm@0: // The PLL needs time to settle or the sample rate will be unstable and possibly andrewm@0: // cause an underrun. Give it ~1ms before going on. andrewm@0: // 10ns per loop iteration = 10^-8s --> 10^5 iterations needed andrewm@0: andrewm@0: MOV r2, 1 << 28 andrewm@0: MOV r3, GPIO1 + GPIO_SETDATAOUT andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: MOV r2, 100000 andrewm@0: MCASP_INIT_WAIT: andrewm@0: SUB r2, r2, 1 andrewm@0: QBNE MCASP_INIT_WAIT, r2, 0 andrewm@0: andrewm@0: MOV r2, 1 << 28 andrewm@0: MOV r3, GPIO1 + GPIO_CLEARDATAOUT andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_RGBLCTL, (1 << 0) // Set RCLKRST andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_XGBLCTL, (1 << 8) // Set XCLKRST andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_RGBLCTL, (1 << 2) // Set RSRCLR andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_XGBLCTL, (1 << 10) // Set XSRCLR andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_RGBLCTL, (1 << 3) // Set RSMRST andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_XGBLCTL, (1 << 11) // Set XSMRST andrewm@0: andrewm@0: MCASP_REG_WRITE_EXT MCASP_XBUF, 0x00 // Write to the transmit buffer to prevent underflow andrewm@0: andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_RGBLCTL, (1 << 4) // Set RFRST andrewm@0: MCASP_REG_SET_BIT_AND_POLL MCASP_XGBLCTL, (1 << 12) // Set XFRST andrewm@0: andrewm@0: // Initialisation andrewm@12: LBBO reg_frame_total, reg_comm_addr, COMM_BUFFER_FRAMES, 4 // Total frame count (SPI; 0.5x-2x for McASP) andrewm@0: MOV reg_dac_buf0, 0 // DAC buffer 0 start pointer andrewm@12: LSL reg_dac_buf1, reg_frame_total, 1 // DAC buffer 1 start pointer = N[ch]*2[bytes]*bufsize andrewm@12: LMBD r2, reg_num_channels, 1 // Returns 1, 2 or 3 depending on the number of channels andrewm@12: LSL reg_dac_buf1, reg_dac_buf1, r2 // Multiply by 2, 4 or 8 to get the N[ch] scaling above andrewm@0: MOV reg_mcasp_buf0, 0 // McASP DAC buffer 0 start pointer andrewm@12: LSL reg_mcasp_buf1, reg_frame_total, r2 // McASP DAC buffer 1 start pointer = 2[ch]*2[bytes]*(N/4)[samples/spi]*bufsize andrewm@0: CLR reg_flags, reg_flags, FLAG_BIT_BUFFER1 // Bit 0 holds which buffer we are on andrewm@0: MOV r2, 0 andrewm@0: SBBO r2, reg_comm_addr, COMM_FRAME_COUNT, 4 // Start with frame count of 0 andrewm@0: andrewm@0: // Here we are out of sync by one TDM slot since the 0 word transmitted above will have occupied andrewm@0: // the first output slot. Send one more word before jumping into the loop. andrewm@0: MCASP_DAC_WAIT_BEFORE_LOOP: andrewm@0: LBBO r2, reg_mcasp_addr, MCASP_XSTAT, 4 andrewm@0: QBBC MCASP_DAC_WAIT_BEFORE_LOOP, r2, MCASP_XSTAT_XDATA_BIT andrewm@0: andrewm@0: MCASP_REG_WRITE_EXT MCASP_XBUF, 0x00 andrewm@0: andrewm@0: // Likewise, read and discard the first sample we get back from the ADC. This keeps the DAC and ADC andrewm@0: // in sync in terms of which TDM slot we are reading (empirically found that we should throw this away andrewm@0: // rather than keep it and invert the phase) andrewm@0: MCASP_ADC_WAIT_BEFORE_LOOP: andrewm@0: LBBO r2, reg_mcasp_addr, MCASP_RSTAT, 4 andrewm@0: QBBC MCASP_ADC_WAIT_BEFORE_LOOP, r2, MCASP_RSTAT_RDATA_BIT andrewm@0: andrewm@0: MCASP_REG_READ_EXT MCASP_RBUF, r2 andrewm@0: andrewm@0: WRITE_ONE_BUFFER: andrewm@0: // Write a single buffer of DAC samples and read a buffer of ADC samples andrewm@0: // Load starting positions andrewm@0: MOV reg_dac_current, reg_dac_buf0 // DAC: reg_dac_current is current pointer andrewm@12: LMBD r2, reg_num_channels, 1 // 1, 2 or 3 for 2, 4 or 8 channels andrewm@12: LSL reg_adc_current, reg_frame_total, r2 andrewm@12: LSL reg_adc_current, reg_adc_current, 2 // N * 2 * 2 * bufsize andrewm@12: ADD reg_adc_current, reg_adc_current, reg_dac_current // ADC: starts N * 2 * 2 * bufsize beyond DAC andrewm@0: MOV reg_mcasp_dac_current, reg_mcasp_buf0 // McASP: set current DAC pointer andrewm@12: LSL reg_mcasp_adc_current, reg_frame_total, r2 // McASP ADC: starts (N/2)*2*2*bufsize beyond DAC andrewm@12: LSL reg_mcasp_adc_current, reg_mcasp_adc_current, 1 andrewm@0: ADC reg_mcasp_adc_current, reg_mcasp_adc_current, reg_mcasp_dac_current andrewm@0: MOV reg_frame_current, 0 andrewm@0: andrewm@0: WRITE_LOOP: andrewm@12: // Write N channels to DAC from successive values in memory andrewm@12: // At the same time, read N channels from ADC andrewm@0: // Unrolled by a factor of 2 to get high and low words andrewm@0: MOV r1, 0 andrewm@0: ADC_DAC_LOOP: andrewm@0: QBBC SPI_DAC_LOAD_DONE, reg_flags, FLAG_BIT_USE_SPI andrewm@0: // Load next 2 SPI DAC samples and store zero in their place andrewm@0: LBCO reg_dac_data, C_ADC_DAC_MEM, reg_dac_current, 4 andrewm@0: MOV r2, 0 andrewm@0: SBCO r2, C_ADC_DAC_MEM, reg_dac_current, 4 andrewm@0: ADD reg_dac_current, reg_dac_current, 4 andrewm@0: SPI_DAC_LOAD_DONE: andrewm@0: andrewm@0: // On even iterations, load two more samples and choose the first one andrewm@0: // On odd iterations, transmit the second of the samples already loaded andrewm@12: // QBBS MCASP_DAC_HIGH_WORD, r1, 1 andrewm@12: QBBS MCASP_DAC_HIGH_WORD, reg_flags, FLAG_BIT_MCASP_HWORD andrewm@0: MCASP_DAC_LOW_WORD: andrewm@0: // Load next 2 Audio DAC samples and store zero in their place andrewm@0: LBCO reg_mcasp_dac_data, C_MCASP_MEM, reg_mcasp_dac_current, 4 andrewm@0: MOV r2, 0 andrewm@0: SBCO r2, C_MCASP_MEM, reg_mcasp_dac_current, 4 andrewm@0: ADD reg_mcasp_dac_current, reg_mcasp_dac_current, 4 andrewm@0: andrewm@0: // Mask out the low word (first in little endian) andrewm@0: MOV r2, 0xFFFF andrewm@0: AND r7, reg_mcasp_dac_data, r2 andrewm@0: andrewm@0: QBA MCASP_WAIT_XSTAT andrewm@0: MCASP_DAC_HIGH_WORD: andrewm@0: // Take the high word of the previously loaded data andrewm@0: LSR r7, reg_mcasp_dac_data, 16 andrewm@0: andrewm@12: // Every 2 channels we send one audio sample; this loop already andrewm@0: // sends exactly two SPI channels. andrewm@0: // Wait for McASP XSTAT[XDATA] to set indicating we can write more data andrewm@0: MCASP_WAIT_XSTAT: andrewm@0: LBBO r2, reg_mcasp_addr, MCASP_XSTAT, 4 andrewm@0: QBBC MCASP_WAIT_XSTAT, r2, MCASP_XSTAT_XDATA_BIT andrewm@0: andrewm@0: MCASP_REG_WRITE_EXT MCASP_XBUF, r7 andrewm@0: andrewm@0: // Same idea with ADC: even iterations, load the sample into the low word, odd andrewm@0: // iterations, load the sample into the high word and store andrewm@12: // QBBS MCASP_ADC_HIGH_WORD, r1, 1 andrewm@12: QBBS MCASP_ADC_HIGH_WORD, reg_flags, FLAG_BIT_MCASP_HWORD andrewm@0: MCASP_ADC_LOW_WORD: andrewm@0: // Start ADC data at 0 andrewm@0: LDI reg_mcasp_adc_data, 0 andrewm@0: andrewm@0: // Now wait for a received word to become available from the audio ADC andrewm@0: MCASP_WAIT_RSTAT_LOW: andrewm@0: LBBO r2, reg_mcasp_addr, MCASP_RSTAT, 4 andrewm@0: QBBC MCASP_WAIT_RSTAT_LOW, r2, MCASP_RSTAT_RDATA_BIT andrewm@0: andrewm@0: // Mask low word and store in ADC data register andrewm@0: MCASP_REG_READ_EXT MCASP_RBUF, r3 andrewm@0: MOV r2, 0xFFFF andrewm@0: AND reg_mcasp_adc_data, r3, r2 andrewm@0: QBA MCASP_ADC_DONE andrewm@0: andrewm@0: MCASP_ADC_HIGH_WORD: andrewm@0: // Wait for a received word to become available from the audio ADC andrewm@0: MCASP_WAIT_RSTAT_HIGH: andrewm@0: LBBO r2, reg_mcasp_addr, MCASP_RSTAT, 4 andrewm@0: QBBC MCASP_WAIT_RSTAT_HIGH, r2, MCASP_RSTAT_RDATA_BIT andrewm@0: andrewm@0: // Read data and shift 16 bits to the left (into the high word) andrewm@0: MCASP_REG_READ_EXT MCASP_RBUF, r3 andrewm@0: LSL r3, r3, 16 andrewm@0: OR reg_mcasp_adc_data, reg_mcasp_adc_data, r3 andrewm@0: andrewm@0: // Now store the result and increment the pointer andrewm@0: SBCO reg_mcasp_adc_data, C_MCASP_MEM, reg_mcasp_adc_current, 4 andrewm@0: ADD reg_mcasp_adc_current, reg_mcasp_adc_current, 4 andrewm@0: MCASP_ADC_DONE: andrewm@0: QBBC SPI_SKIP_WRITE, reg_flags, FLAG_BIT_USE_SPI andrewm@0: andrewm@0: // DAC: transmit low word (first in little endian) andrewm@0: MOV r2, 0xFFFF andrewm@0: AND r7, reg_dac_data, r2 andrewm@0: LSL r7, r7, AD5668_DATA_OFFSET andrewm@0: MOV r8, (0x03 << AD5668_COMMAND_OFFSET) andrewm@0: OR r7, r7, r8 andrewm@0: LSL r8, r1, AD5668_ADDRESS_OFFSET andrewm@0: OR r7, r7, r8 andrewm@0: DAC_WRITE r7 andrewm@0: andrewm@0: // Read ADC channels: result is always 2 commands behind andrewm@0: // Start by reading channel 2 (result is channel 0) and go andrewm@12: // to N+2, but masking the channel number to be between 0 and N-1 andrewm@0: LDI reg_adc_data, 0 andrewm@12: ADD r8, r1, 2 andrewm@12: SUB r7, reg_num_channels, 1 andrewm@12: AND r8, r8, r7 andrewm@12: LSL r8, r8, AD7699_CHANNEL_OFFSET andrewm@0: MOV r7, AD7699_CFG_MASK andrewm@0: OR r7, r7, r8 andrewm@0: ADC_WRITE r7, r7 andrewm@0: andrewm@0: // Mask out only the relevant 16 bits and store in reg_adc_data andrewm@0: MOV r2, 0xFFFF andrewm@0: AND reg_adc_data, r7, r2 andrewm@0: andrewm@0: // Increment channel index andrewm@0: ADD r1, r1, 1 andrewm@0: andrewm@0: // DAC: transmit high word (second in little endian) andrewm@0: LSR r7, reg_dac_data, 16 andrewm@0: LSL r7, r7, AD5668_DATA_OFFSET andrewm@0: MOV r8, (0x03 << AD5668_COMMAND_OFFSET) andrewm@0: OR r7, r7, r8 andrewm@0: LSL r8, r1, AD5668_ADDRESS_OFFSET andrewm@0: OR r7, r7, r8 andrewm@0: DAC_WRITE r7 andrewm@0: andrewm@0: // Read ADC channels: result is always 2 commands behind andrewm@0: // Start by reading channel 2 (result is channel 0) and go andrewm@12: // to N+2, but masking the channel number to be between 0 and N-1 andrewm@12: LDI reg_adc_data, 0 andrewm@12: ADD r8, r1, 2 andrewm@12: SUB r7, reg_num_channels, 1 andrewm@12: AND r8, r8, r7 andrewm@12: LSL r8, r8, AD7699_CHANNEL_OFFSET andrewm@0: MOV r7, AD7699_CFG_MASK andrewm@0: OR r7, r7, r8 andrewm@0: ADC_WRITE r7, r7 andrewm@0: andrewm@0: // Move this result up to the 16 high bits andrewm@0: LSL r7, r7, 16 andrewm@0: OR reg_adc_data, reg_adc_data, r7 andrewm@0: andrewm@0: // Store 2 ADC words in memory andrewm@0: SBCO reg_adc_data, C_ADC_DAC_MEM, reg_adc_current, 4 andrewm@0: ADD reg_adc_current, reg_adc_current, 4 andrewm@0: andrewm@12: // Toggle the high/low word for McASP control (since we send one word out of andrewm@12: // 32 bits for each pair of SPI channels) andrewm@12: XOR reg_flags, reg_flags, (1 << FLAG_BIT_MCASP_HWORD) andrewm@12: andrewm@12: // Repeat 4 times for 8 channels (2 samples per loop, r1 += 1 already happened) andrewm@12: // For 4 or 2 channels, repeat 2 or 1 times, according to flags andrewm@0: ADD r1, r1, 1 andrewm@12: QBNE ADC_DAC_LOOP, r1, reg_num_channels andrewm@0: QBA ADC_DAC_LOOP_DONE andrewm@12: andrewm@0: SPI_SKIP_WRITE: andrewm@0: // We get here only if the SPI ADC and DAC are disabled andrewm@0: // Just keep the loop going for McASP andrewm@12: andrewm@12: // Toggle the high/low word for McASP control (since we send one word out of andrewm@12: // 32 bits for each pair of SPI channels) andrewm@12: XOR reg_flags, reg_flags, (1 << FLAG_BIT_MCASP_HWORD) andrewm@12: andrewm@0: ADD r1, r1, 2 andrewm@12: QBNE ADC_DAC_LOOP, r1, reg_num_channels andrewm@0: andrewm@0: ADC_DAC_LOOP_DONE: andrewm@0: // Increment number of frames, see if we have more to write andrewm@0: ADD reg_frame_current, reg_frame_current, 1 andrewm@0: QBNE WRITE_LOOP, reg_frame_current, reg_frame_total andrewm@0: andrewm@0: WRITE_LOOP_DONE: andrewm@0: // Now done, swap the buffers and do the next one andrewm@0: // Use r2 as a temp register andrewm@0: MOV r2, reg_dac_buf0 andrewm@0: MOV reg_dac_buf0, reg_dac_buf1 andrewm@0: MOV reg_dac_buf1, r2 andrewm@0: MOV r2, reg_mcasp_buf0 andrewm@0: MOV reg_mcasp_buf0, reg_mcasp_buf1 andrewm@0: MOV reg_mcasp_buf1, r2 andrewm@0: andrewm@0: // Notify ARM of buffer swap andrewm@0: XOR reg_flags, reg_flags, (1 << FLAG_BIT_BUFFER1) andrewm@0: AND r2, reg_flags, (1 << FLAG_BIT_BUFFER1) // Mask out every but low bit andrewm@0: SBBO r2, reg_comm_addr, COMM_CURRENT_BUFFER, 4 andrewm@0: andrewm@0: // Increment the frame count in the comm buffer (for status monitoring) andrewm@0: LBBO r2, reg_comm_addr, COMM_FRAME_COUNT, 4 andrewm@0: ADD r2, r2, reg_frame_total andrewm@0: SBBO r2, reg_comm_addr, COMM_FRAME_COUNT, 4 andrewm@0: andrewm@0: // If LED blink enabled, toggle every 4096 frames andrewm@0: LBBO r3, reg_comm_addr, COMM_LED_ADDRESS, 4 andrewm@0: QBEQ LED_BLINK_DONE, r3, 0 andrewm@0: MOV r1, 0x1000 andrewm@0: AND r2, r2, r1 // Test (frame count & 4096) andrewm@0: QBEQ LED_BLINK_OFF, r2, 0 andrewm@0: LBBO r2, reg_comm_addr, COMM_LED_PIN_MASK, 4 andrewm@0: MOV r1, GPIO_SETDATAOUT andrewm@0: ADD r3, r3, r1 // Address for GPIO set register andrewm@0: SBBO r2, r3, 0, 4 // Set GPIO pin andrewm@0: QBA LED_BLINK_DONE andrewm@0: LED_BLINK_OFF: andrewm@0: LBBO r2, reg_comm_addr, COMM_LED_PIN_MASK, 4 andrewm@0: MOV r1, GPIO_CLEARDATAOUT andrewm@0: ADD r3, r3, r1 // Address for GPIO clear register andrewm@0: SBBO r2, r3, 0, 4 // Clear GPIO pin andrewm@0: LED_BLINK_DONE: andrewm@0: andrewm@0: QBBC TESTLOW, reg_flags, FLAG_BIT_BUFFER1 andrewm@0: MOV r2, 1 << 28 andrewm@0: MOV r3, GPIO1 + GPIO_SETDATAOUT andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: QBA TESTDONE andrewm@0: TESTLOW: andrewm@0: MOV r2, 1 << 28 andrewm@0: MOV r3, GPIO1 + GPIO_CLEARDATAOUT andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: TESTDONE: andrewm@0: andrewm@0: // Check if we should finish: flag is zero as long as it should run andrewm@0: LBBO r2, reg_comm_addr, COMM_SHOULD_STOP, 4 andrewm@0: QBEQ WRITE_ONE_BUFFER, r2, 0 andrewm@0: andrewm@0: CLEANUP: andrewm@0: MCASP_REG_WRITE MCASP_GBLCTL, 0x00 // Turn off McASP andrewm@0: andrewm@0: // Turn off SPI if enabled andrewm@0: QBBC SPI_CLEANUP_DONE, reg_flags, FLAG_BIT_USE_SPI andrewm@0: andrewm@0: MOV r3, SPI_BASE + SPI_CH0CONF andrewm@0: LBBO r2, r3, 0, 4 andrewm@0: CLR r2, r2, 13 andrewm@0: CLR r2, r2, 27 andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: andrewm@0: MOV r3, SPI_BASE + SPI_CH0CTRL andrewm@0: LBBO r2, r3, 0, 4 andrewm@0: CLR r2, r2, 1 andrewm@0: SBBO r2, r3, 0, 4 andrewm@0: SPI_CLEANUP_DONE: andrewm@0: andrewm@0: // Signal the ARM that we have finished andrewm@0: MOV R31.b0, PRU0_ARM_INTERRUPT + 16 andrewm@0: HALT