diff pru_rtaudio.p @ 19:c98863e63174 matrix_gpio

Renamed matrixGpio to digital and matrix to analog

--- a/pru_rtaudio.p	Thu Apr 30 16:02:47 2015 +0100
+++ b/pru_rtaudio.p	Thu Apr 30 16:58:41 2015 +0100
@@ -81,7 +81,7 @@
 #define COMM_FRAME_COUNT      32	  // How many frames have elapse since beginning
 #define COMM_USE_SPI          36          // Whether or not to use SPI ADC and DAC
 #define COMM_NUM_CHANNELS     40	  // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels
-#define COMM_USE_MATRIX_GPIO  44	  // Whether or not to use MATRIX_GPIO
+#define COMM_USE_DIGITAL  44	  // Whether or not to use DIGITAL
 
 #define MCASP0_BASE 0x48038000
 #define MCASP1_BASE 0x4803C000
@@ -181,18 +181,18 @@
 #define FLAG_BIT_BUFFER1	0
 #define FLAG_BIT_USE_SPI	1
 #define FLAG_BIT_MCASP_HWORD	2		// Whether we are on the high word for McASP transmission
-#define FLAG_BIT_USE_MATRIX_GPIO 3
-/*#define FLAG_BIT_MATRIX_GPIO_BUFFER 4 //Whether we are using buffer located at
-                                     // 0:  MEM_MATRIX_GPIO_BASE or
-*/                                     // 1: MEM_MATRIX_GPIO_BASE + 512
+#define FLAG_BIT_USE_DIGITAL 3
+/*#define FLAG_BIT_DIGITAL_BUFFER 4 //Whether we are using buffer located at
+                                     // 0:  MEM_DIGITAL_BASE or
+*/                                     // 1: MEM_DIGITAL_BASE + 512
 // Registers used throughout
 
 // r1, r2, r3 are used for temporary storage
-#define MEM_MATRIX_GPIO_BASE 0x11000 //Base address for MATRIX_GPIO : Shared RAM + 0x400
-#define MEM_MATRIX_GPIO_BUFFER1_OFFSET 0x400 //Start pointer to MATRIX_GPIO_BUFFER1, which is 256 words after.
+#define MEM_DIGITAL_BASE 0x11000 //Base address for DIGITAL : Shared RAM + 0x400
+#define MEM_DIGITAL_BUFFER1_OFFSET 0x400 //Start pointer to DIGITAL_BUFFER1, which is 256 words after.
 // 256 is the maximum number of frames allowed
 
-#define reg_matrix_gpio_current r6  // Pointer to current storage location of MATRIX_GPIO
+#define reg_digital_current r6  // Pointer to current storage location of DIGITAL
 #define reg_num_channels	r9		// Number of SPI ADC/DAC channels to use
 #define reg_frame_current	r10		// Current frame count in SPI ADC/DAC transfer
 #define reg_frame_total		r11		// Total frame count for SPI ADC/DAC
@@ -214,7 +214,7 @@
 // r27, r28 used in macros
 #define reg_mcasp_addr		r29		// Base address for McASP
 
-// MATRIX_GPIO new code starts here
+// DIGITAL new code starts here
 //0  P8_07 36 0x890/090 66 gpio2[2]
 //1  P8_08 37 0x894/094 67 gpio2[3]
 //2  P8_09 39 0x89c/09c 69 gpio2[5]
@@ -249,50 +249,50 @@
 #define reg_gpio2_setdataout r5
 #define reg_gpio1_cleardataout r7
 #define reg_gpio1_setdataout r8
-#define reg_matrix_gpio r27 //will first contain matrixGpioOut from render() and matrixGpioIn to render() later
+#define reg_digital r27 //will first contain digitalOut from render() and digitalIn to render() later
 //aliases
 #define reg_gpio1_datain reg_gpio1_oe
 #define reg_gpio2_datain reg_gpio2_oe
 
 .macro SET_GPIO1_BITS
-.mparam gpio_num_bit, matrix_gpio_bit
-    SET_GPIO_BITS reg_gpio1_oe, reg_gpio1_setdataout, reg_gpio1_cleardataout, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+.mparam gpio_num_bit, digital_bit
+    SET_GPIO_BITS reg_gpio1_oe, reg_gpio1_setdataout, reg_gpio1_cleardataout, gpio_num_bit, digital_bit, reg_digital
 .endm
 .macro SET_GPIO2_BITS
-.mparam gpio_num_bit, matrix_gpio_bit
-    SET_GPIO_BITS reg_gpio2_oe, reg_gpio2_setdataout, reg_gpio2_cleardataout, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+.mparam gpio_num_bit, digital_bit
+    SET_GPIO_BITS reg_gpio2_oe, reg_gpio2_setdataout, reg_gpio2_cleardataout, gpio_num_bit, digital_bit, reg_digital
 .endm
 .macro READ_GPIO1_BITS
-.mparam gpio_num_bit, matrix_gpio_bit
-    READ_GPIO_BITS reg_gpio1_datain, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+.mparam gpio_num_bit, digital_bit
+    READ_GPIO_BITS reg_gpio1_datain, gpio_num_bit, digital_bit, reg_digital
 .endm
 .macro READ_GPIO2_BITS
-.mparam gpio_num_bit, matrix_gpio_bit
-    READ_GPIO_BITS reg_gpio2_datain, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+.mparam gpio_num_bit, digital_bit
+    READ_GPIO_BITS reg_gpio2_datain, gpio_num_bit, digital_bit, reg_digital
 .endm
 
 .macro READ_GPIO_BITS
-.mparam gpio_data, gpio_num_bit, matrix_gpio_bit, matrix_gpio
-    QBBC DONE, matrix_gpio, matrix_gpio_bit //if the pin is set as an output, nothing to do here
+.mparam gpio_data, gpio_num_bit, digital_bit, digital
+    QBBC DONE, digital, digital_bit //if the pin is set as an output, nothing to do here
 SET r30.t14
     QBBC CLEAR, gpio_data, gpio_num_bit 
-    SET matrix_gpio, matrix_gpio_bit+16
+    SET digital, digital_bit+16
     QBA DONE
     CLEAR:
-        CLR matrix_gpio, matrix_gpio_bit+16
+        CLR digital, digital_bit+16
         QBA DONE
     DONE:
 CLR r30.t14
 .endm
 
 .macro SET_GPIO_BITS
-.mparam gpio_oe, gpio_setdataout, gpio_cleardataout, gpio_num_bit, matrix_gpio_bit, matrix_gpio //sets the bits in GPIO_OE, GPIO_SETDATAOUT and GPIO_CLEARDATAOUT
+.mparam gpio_oe, gpio_setdataout, gpio_cleardataout, gpio_num_bit, digital_bit, digital //sets the bits in GPIO_OE, GPIO_SETDATAOUT and GPIO_CLEARDATAOUT
 //Remember that the GPIO_OE Output data enable register behaves as follows for each bit:
 //0 = The corresponding GPIO pin is configured as an output.
 //1 = The corresponding GPIO pin is configured as an input.
-    QBBS SETINPUT, matrix_gpio, matrix_gpio_bit 
+    QBBS SETINPUT, digital, digital_bit 
     CLR gpio_oe, gpio_num_bit //if it is an output, configure pin as output
-    QBBC CLEARDATAOUT, matrix_gpio, matrix_gpio_bit+16 // check the output value. If it is 0, branch
+    QBBC CLEARDATAOUT, digital, digital_bit+16 // check the output value. If it is 0, branch
     SET gpio_setdataout, gpio_num_bit //if it is 1, set output to high
     QBA DONE
 CLEARDATAOUT:
@@ -306,25 +306,25 @@
 
 .macro PROCESS_GPIO1_BITS
 //- sets appropriate bits for output in reg_gpio1_oe, reg_gpio1_cleardataout, reg_gpio1_data
-//- sets appropriate bits in reg_matrix_gpio to reflect the input values
-.mparam gpio_num_bit, matrix_gpio_bit
-// params to SET_GPIO_BITS gpio_oe, gpio_setdataout, gpio_cleardataout, gpio_num_bit, matrix_gpio_bit, matrix_gpio //sets the bits in GPIO_OE, GPIO_SETDATAOUT and GPIO_CLEARDATAOUT
-    SET_GPIO_BITS reg_gpio1_oe, reg_gpio1_setdataout, reg_gpio1_cleardataout, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
-    READ_GPIO_BITS reg_gpio1_oe, reg_gpio1_datain, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+//- sets appropriate bits in reg_digital to reflect the input values
+.mparam gpio_num_bit, digital_bit
+// params to SET_GPIO_BITS gpio_oe, gpio_setdataout, gpio_cleardataout, gpio_num_bit, digital_bit, digital //sets the bits in GPIO_OE, GPIO_SETDATAOUT and GPIO_CLEARDATAOUT
+    SET_GPIO_BITS reg_gpio1_oe, reg_gpio1_setdataout, reg_gpio1_cleardataout, gpio_num_bit, digital_bit, reg_digital
+    READ_GPIO_BITS reg_gpio1_oe, reg_gpio1_datain, gpio_num_bit, digital_bit, reg_digital
 .endm
 
 .macro PROCESS_GPIO2_BITS
 //- sets appropriate bits for output in reg_gpio2_oe, reg_gpio2_cleardataout, reg_gpio2_data
-//- sets appropriate bits in reg_matrix_gpio to reflect the input values
-.mparam gpio_num_bit, matrix_gpio_bit
-    SET_GPIO_BITS reg_gpio2_oe, reg_gpio2_setdataout, reg_gpio2_cleardataout, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
-    READ_GPIO_BITS reg_gpio2_oe, reg_gpio2_datain, gpio_num_bit, matrix_gpio_bit, reg_matrix_gpio
+//- sets appropriate bits in reg_digital to reflect the input values
+.mparam gpio_num_bit, digital_bit
+    SET_GPIO_BITS reg_gpio2_oe, reg_gpio2_setdataout, reg_gpio2_cleardataout, gpio_num_bit, digital_bit, reg_digital
+    READ_GPIO_BITS reg_gpio2_oe, reg_gpio2_datain, gpio_num_bit, digital_bit, reg_digital
 .endm
 
 QBA START // when first starting, go to START, skipping this section.
 
-MATRIX_GPIO:
-//reg_matrix_gpio is now the input word passed in render(), one word per frame
+DIGITAL:
+//reg_digital is now the input word passed in render(), one word per frame
 //[31:16]: data(1=high, 0=low), [15:0]: direction (0=output, 1=input) )
 //Preparing the gpio_oe, gpio_cleardataout and gpio_setdataout for each module
 
@@ -336,7 +336,7 @@
 //process oe and datain and prepare dataout for GPIO1
     LDI reg_gpio1_setdataout, 0 
     LDI reg_gpio1_cleardataout, 0
-//map GPIO_MATRIX to gpio1 pins, affects reg_gpio1_oe, reg_gpio1_cleardataout, reg_gpio1_data, reg_matrix_gpio
+//map GPIO_ANALOG to gpio1 pins, affects reg_gpio1_oe, reg_gpio1_cleardataout, reg_gpio1_data, reg_digital
     SET_GPIO1_BITS 13, 4
     SET_GPIO1_BITS 12, 5
     SET_GPIO1_BITS 28, 6
@@ -359,7 +359,7 @@
 //process oe and datain and prepare dataout for GPIO2
     LDI reg_gpio2_setdataout, 0 
     LDI reg_gpio2_cleardataout, 0
-//map GPIO_MATRIX to gpio2 pins, affects reg_gpio2_oe, reg_gpio2_cleardataout, reg_gpio2_data, reg_matrix_gpio
+//map GPIO_ANALOG to gpio2 pins, affects reg_gpio2_oe, reg_gpio2_cleardataout, reg_gpio2_data, reg_digital
     SET_GPIO2_BITS 2, 0
     SET_GPIO2_BITS 3, 1
     SET_GPIO2_BITS 5, 2
@@ -415,7 +415,7 @@
 //regardless of whether the order is gpio1-gpio2 or gpio2-gpio1
 JMP r28.w0 // go back to ADC_WRITE_GPIO
 
-// MATRIX_GPIO new code ends here
+// DIGITAL new code ends here
 
 	
 // Bring CS line low to write to DAC
@@ -503,24 +503,24 @@
       ADC_CS_UNASSERT
 .endm
 
-// Complete ADC write+read with chip select and also performs IO for matrix_gpio
+// Complete ADC write+read with chip select and also performs IO for digital
 .macro ADC_WRITE_GPIO
 .mparam in, out, do_gpio
       ADC_CS_ASSERT
       ADC_TX in
-      QBBC GPIO_DONE, reg_flags, FLAG_BIT_USE_MATRIX_GPIO //skip if MATRIX_GPIO is disabled
-      AND r27, do_gpio, 0x3 // only do a MATRIX_GPIO every 2 SPI I/O
+      QBBC GPIO_DONE, reg_flags, FLAG_BIT_USE_DIGITAL //skip if DIGITAL is disabled
+      AND r27, do_gpio, 0x3 // only do a DIGITAL every 2 SPI I/O
       QBNE GPIO_DONE, r27, 0 
 //from here to GPIO_DONE takes 1.8us, while usually ADC_WAIT_FOR_FINISH only waits for 1.14us.
-//TODO: it would be better to split the MATRIX_GPIO stuff in two parts:
+//TODO: it would be better to split the DIGITAL stuff in two parts:
 //- one taking place during DAC_WRITE which sets the GPIO_OE
 //- and the other during ADC_WRITE which actually reads DATAIN and writes CLEAR/SET DATAOUT
-                            //reg_matrix_gpio is actually r27, so do not use r27 from here to ...
-      LBBO reg_matrix_gpio, reg_matrix_gpio_current, 0, 4 
-      JAL r28.w0, MATRIX_GPIO
-      SBBO reg_matrix_gpio, reg_matrix_gpio_current, 0,   4 
+                            //reg_digital is actually r27, so do not use r27 from here to ...
+      LBBO reg_digital, reg_digital_current, 0, 4 
+      JAL r28.w0, DIGITAL
+      SBBO reg_digital, reg_digital_current, 0,   4 
                             //..here you can start using r27 again
-      ADD reg_matrix_gpio_current, reg_matrix_gpio_current, 4 //increment pointer
+      ADD reg_digital_current, reg_digital_current, 4 //increment pointer
 GPIO_DONE:
       ADC_WAIT_FOR_FINISH
       ADC_RX out
@@ -599,12 +599,12 @@
       // Default number of channels in case SPI disabled
       LDI reg_num_channels, 8
 	
-      // Find out whether we should use MATRIX_GPIO
-      LBBO r2, reg_comm_addr, COMM_USE_MATRIX_GPIO, 4
-      QBEQ MATRIX_GPIO_FLAG_CHECK_DONE, r2, 0
-      SET reg_flags, reg_flags, FLAG_BIT_USE_MATRIX_GPIO
-//      SET reg_flags, reg_flags, FLAG_BIT_MATRIX_GPIO_BUFFER //set the flag, so that in WRITE_ONE_BUFFER we will start from buffer0
-MATRIX_GPIO_FLAG_CHECK_DONE:
+      // Find out whether we should use DIGITAL
+      LBBO r2, reg_comm_addr, COMM_USE_DIGITAL, 4
+      QBEQ DIGITAL_FLAG_CHECK_DONE, r2, 0
+      SET reg_flags, reg_flags, FLAG_BIT_USE_DIGITAL
+//      SET reg_flags, reg_flags, FLAG_BIT_DIGITAL_BUFFER //set the flag, so that in WRITE_ONE_BUFFER we will start from buffer0
+DIGITAL_FLAG_CHECK_DONE:
       // Find out whether we should use SPI ADC and DAC
       LBBO r2, reg_comm_addr, COMM_USE_SPI, 4
       QBEQ SPI_FLAG_CHECK_DONE, r2, 0
@@ -795,15 +795,15 @@
       LSL reg_mcasp_adc_current, reg_mcasp_adc_current, 1
       ADC reg_mcasp_adc_current, reg_mcasp_adc_current, reg_mcasp_dac_current
       MOV reg_frame_current, 0
-      QBBS MATRIX_GPIO_BASE_CHECK_SET, reg_flags, FLAG_BIT_BUFFER1  //check which buffer we are using for MATRIX_GPIO
+      QBBS DIGITAL_BASE_CHECK_SET, reg_flags, FLAG_BIT_BUFFER1  //check which buffer we are using for DIGITAL
                   // if we are here, we are using buffer0 
       MOV r2, 0  //so adjust offset appropriately
-      QBA MATRIX_GPIO_BASE_CHECK_DONE
-MATRIX_GPIO_BASE_CHECK_SET: //if we are here, we are using buffer1 
-      MOV r2, MEM_MATRIX_GPIO_BUFFER1_OFFSET //so adjust offset appropriately
-MATRIX_GPIO_BASE_CHECK_DONE:
-      MOV reg_matrix_gpio_current, MEM_MATRIX_GPIO_BASE
-      ADD reg_matrix_gpio_current, reg_matrix_gpio_current, r2
+      QBA DIGITAL_BASE_CHECK_DONE
+DIGITAL_BASE_CHECK_SET: //if we are here, we are using buffer1 
+      MOV r2, MEM_DIGITAL_BUFFER1_OFFSET //so adjust offset appropriately
+DIGITAL_BASE_CHECK_DONE:
+      MOV reg_digital_current, MEM_DIGITAL_BASE
+      ADD reg_digital_current, reg_digital_current, r2
 
 CLR r30.t15
 WRITE_LOOP: