comparison pru_rtaudio.p @ 346:c6a15a8dee02 prerelease

Remapped analog output channels to match 01234567 order on cape. Note: this will change the behaviour of all these existing examples using analog out, notably d-box and cape_test.

 #define COMM_USE_SPI          36          // Whether or not to use SPI ADC and DAC
 #define COMM_NUM_CHANNELS     40	  // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels
 #define COMM_USE_DIGITAL      44	  // Whether or not to use DIGITAL
 #define COMM_PRU_NUMBER       48          // Which PRU this code is running on
 #define COMM_MUX_CONFIG       52          // Whether to use the mux capelet, and how many channels
-
+#define COMM_MUX_END_CHANNEL  56          // Which mux channel the last buffer ended on
+	
 // General constants for McASP peripherals (used for audio codec)
 #define MCASP0_BASE 0x48038000
 #define MCASP1_BASE 0x4803C000
 
 #define MCASP_PWRIDLESYSCONFIG 		0x04

 #define FLAG_BIT_USE_DIGITAL	3
 	
 #define FLAG_BIT_MUX_CONFIG0	 8		// Mux capelet configuration:
 #define FLAG_BIT_MUX_CONFIG1	 9		// 00 = off, 01 = 2 ch., 10 = 4 ch., 11 = 8 ch.
 #define FLAG_MASK_MUX_CONFIG	 0x0300
-	
-#define FLAG_BIT_MUX_STATE0	10		// Current state of the mux channels
-#define FLAG_BIT_MUX_STATE1	11
-#define FLAG_BIT_MUX_STATE2	12
-#define FLAG_MASK_MUX_STATE	0x1C00
-	
+		
 // Registers used throughout
 
 // r1, r2, r3 are used for temporary storage
 #define MEM_DIGITAL_BASE 0x11000 //Base address for DIGITAL : Shared RAM + 0x400
 #define MEM_DIGITAL_BUFFER1_OFFSET 0x400 //Start pointer to DIGITAL_BUFFER1, which is 256 words after.

      DAC_WAIT_FOR_FINISH
      DAC_CS_UNASSERT
      DAC_DISCARD_RX
 .endm
 
+// Transform channel order on DAC
+// (in) 01234567 --> (out) 64201357
+// This is to make the pin order on the Bela cape
+// make sense
+.macro DAC_CHANNEL_REORDER
+.mparam out, in
+     QBBS DAC_CHANNEL_REORDER_HIGH, in, 2
+// Input channels 0,1,2,3 --> 6,4,2,0
+// out = (3 - in) << 1
+     XOR out, in, 0x03
+     LSL out, out, 1
+     QBA DAC_CHANNEL_REORDER_DONE
+DAC_CHANNEL_REORDER_HIGH:	
+// Input channels 4,5,6,7 --> 1,3,5,7
+// out = ((in & 0x03) << 1) + 1
+     AND out, in, 0x03
+     LSL out, out, 1
+     ADD out, out, 1
+DAC_CHANNEL_REORDER_DONE:	
+.endm
+	
 // Bring CS line low to write to ADC
 .macro ADC_CS_ASSERT
      MOV r27, ADC_CS_PIN
      MOV r28, ADC_GPIO + GPIO_CLEARDATAOUT
      SBBO r27, r28, 0, 4

      MOV r2, 0xFFFF
      AND r7, reg_dac_data, r2
      LSL r7, r7, AD5668_DATA_OFFSET
      MOV r8, (0x03 << AD5668_COMMAND_OFFSET)
      OR r7, r7, r8
-     LSL r8, r1, AD5668_ADDRESS_OFFSET
+     DAC_CHANNEL_REORDER r8, r1
+     LSL r8, r8, AD5668_ADDRESS_OFFSET
      OR r7, r7, r8
      DAC_WRITE r7
 
      // Read ADC channels: result is always 2 commands behind
      // Start by reading channel 2 (result is channel 0) and go

      // DAC: transmit high word (second in little endian)
      LSR r7, reg_dac_data, 16
      LSL r7, r7, AD5668_DATA_OFFSET
      MOV r8, (0x03 << AD5668_COMMAND_OFFSET)
      OR r7, r7, r8
-     LSL r8, r1, AD5668_ADDRESS_OFFSET
+     DAC_CHANNEL_REORDER r8, r1
+     LSL r8, r8, AD5668_ADDRESS_OFFSET
      OR r7, r7, r8
      DAC_WRITE r7
 
      // Read ADC channels: result is always 2 commands behind
      // Start by reading channel 2 (result is channel 0) and go

      MOV r2, reg_mcasp_buf0
      MOV reg_mcasp_buf0, reg_mcasp_buf1
      MOV reg_mcasp_buf1, r2
      XOR reg_flags, reg_flags, (1 << FLAG_BIT_BUFFER1) //flip the buffer flag
 
+     // If multiplexer capelet is enabled, save which channel we got to
+     // Muxes 0-3 change at a different time than muxes 4-7 but the first
+     // of these is sufficient to capture where we are
+     MOV r2, FLAG_MASK_MUX_CONFIG
+     AND r2, reg_flags, r2             
+     QBEQ MUX_CHANNEL_SAVE_DONE, r2, 0
+     AND r2, reg_pru1_mux_pins, 0x03
+     SBBO r2, reg_comm_addr, COMM_MUX_END_CHANNEL, 4
+MUX_CHANNEL_SAVE_DONE:	
+	
      // Notify ARM of buffer swap
      AND r2, reg_flags, (1 << FLAG_BIT_BUFFER1)    // Mask out every but low bit
      SBBO r2, reg_comm_addr, COMM_CURRENT_BUFFER, 4
      MOV R31.b0, PRU1_ARM_INTERRUPT + 16           // Interrupt to host loop