comparison pru_rtaudio.p @ 26:6d64ee8c0754 matrix_gpio

- fixed bug that caused the PRU to hang when opening a socket or an ssh connection. Bug was a typo in  LBBO reg_gpio2_oe

 .endm
 
 .macro READ_GPIO_BITS
 .mparam gpio_data, gpio_num_bit, digital_bit, digital
     QBBC DONE, digital, digital_bit //if the pin is set as an output, nothing to do here
-SET r30.t14
     QBBC CLEAR, gpio_data, gpio_num_bit 
     SET digital, digital_bit+16
     QBA DONE
     CLEAR:
         CLR digital, digital_bit+16
         QBA DONE
     DONE:
-CLR r30.t14
 .endm
 
 .macro SET_GPIO_BITS
 .mparam gpio_oe, gpio_setdataout, gpio_cleardataout, gpio_num_bit, digital_bit, digital //sets the bits in GPIO_OE, GPIO_SETDATAOUT and GPIO_CLEARDATAOUT
 //Remember that the GPIO_OE Output data enable register behaves as follows for each bit:

 //[31:16]: data(1=high, 0=low), [15:0]: direction (0=output, 1=input) )
 //Preparing the gpio_oe, gpio_cleardataout and gpio_setdataout for each module
 
 //load current status of GPIO_OE in reg_gpioX_oe
     MOV reg_gpio1_oe, GPIO1 | GPIO_OE 
-    //takes ...ns to go through the next two instructions
+    //it takes 190ns to go through the next instruction
     LBBO reg_gpio1_oe, reg_gpio1_oe, 0, 4
 //GPIO1-start
 //process oe and datain and prepare dataout for GPIO1
     LDI reg_gpio1_setdataout, 0 
     LDI reg_gpio1_cleardataout, 0

 
 // reg_gpio1_oe is now unused, its register is taken by gpio2_cleardataout
 // reg_gpio1_datain now unused, its register is taken by gpio2_setdataout
 //GPIO2-start
 //load current status of GPIO_OE in reg_gpioX_oe
-    MOV reg_gpio2_oe, GPIO2 | GPIO_OE 
-    //takes ...ns to go through the next two instructions
-    LBBO reg_gpio2_oe, reg_gpio1_oe, 0, 4
+    MOV reg_gpio2_oe, GPIO2 | GPIO_OE  
+//it takes 200ns to go through the next instructions
+    LBBO reg_gpio2_oe, reg_gpio2_oe, 0, 4
 //process oe and datain and prepare dataout for GPIO2
     LDI reg_gpio2_setdataout, 0 
     LDI reg_gpio2_cleardataout, 0
 //map GPIO_ANALOG to gpio2 pins, affects reg_gpio2_oe, reg_gpio2_cleardataout, reg_gpio2_data, reg_digital
     SET_GPIO2_BITS 2, 0

 //GPIO2-end
 
 //load current inputs in reg_gpioX_datain
     MOV reg_gpio1_datain, GPIO1 | GPIO_DATAIN 
     MOV reg_gpio2_datain, GPIO2 | GPIO_DATAIN 
-    //takes ...ns to go through the next two instructions
+    //takes 375 nns to go through the next two instructions
     LBBO reg_gpio1_datain, reg_gpio1_datain, 0, 4
     LBBO reg_gpio2_datain, reg_gpio2_datain, 0, 4
-//TODO: read inputs
     READ_GPIO1_BITS 13, 4
     READ_GPIO1_BITS 12, 5
     READ_GPIO1_BITS 28, 6
     READ_GPIO1_BITS 18, 7
     READ_GPIO1_BITS 15, 8

 //We can do this because we chose reg_gpio1_cleardataout and reg_gpioX_setdataout to be consecutive
 //load the memory addresses to be written to
     MOV reg_gpio1_datain, GPIO1 | GPIO_CLEARDATAOUT //reg_gpio1_datain is now unused and is used here as a temp
     MOV reg_gpio2_datain, GPIO2 | GPIO_CLEARDATAOUT //reg_gpio2_datain is now unused and is used here as a temp
 //write 8 bytes for each GPIO
-//takes 30ns in total to go through the followint two lines
+//takes 30ns in total to go through the following two lines
     SBBO reg_gpio1_cleardataout, reg_gpio1_datain, 0, 8 // takes 145ns to be effective when going low, 185ns when going high
     SBBO reg_gpio2_cleardataout, reg_gpio2_datain, 0, 8 //takes 95ns to be effective when going low, 130ns when going high
 //reversing the order of the two lines above will swap the performances between the GPIO modules
 //i.e.: the first line will always take 145ns/185ns and the second one will always take 95ns/130ns, 
 //regardless of whether the order is gpio1-gpio2 or gpio2-gpio1

       AND r28, r28, r27
       QBEQ POLL, r28, 0
 .endm
    
 START:
-      MOV r30, 0 
       // Set up c24 and c25 offsets with CTBIR register
       // Thus C24 points to start of PRU0 RAM
       MOV r3, 0x22020       // CTBIR0
       MOV r2, 0
       SBBO r2, r3, 0, 4

       MCASP_REG_READ_EXT MCASP_RBUF, r2
 	
 WRITE_ONE_BUFFER:
       // Write a single buffer of DAC samples and read a buffer of ADC samples
       // Load starting positions
-SET r30.t15
       MOV reg_dac_current, reg_dac_buf0         // DAC: reg_dac_current is current pointer
       LMBD r2, reg_num_channels, 1		// 1, 2 or 3 for 2, 4 or 8 channels
       LSL reg_adc_current, reg_frame_total, r2
       LSL reg_adc_current, reg_adc_current, 2   // N * 2 * 2 * bufsize
       ADD reg_adc_current, reg_adc_current, reg_dac_current // ADC: starts N * 2 * 2 * bufsize beyond DAC

       MOV r2, MEM_DIGITAL_BUFFER1_OFFSET //so adjust offset appropriately
 DIGITAL_BASE_CHECK_DONE:
       MOV reg_digital_current, MEM_DIGITAL_BASE
       ADD reg_digital_current, reg_digital_current, r2
 
-CLR r30.t15
 WRITE_LOOP:
       // Write N channels to DAC from successive values in memory
       // At the same time, read N channels from ADC
       // Unrolled by a factor of 2 to get high and low words
       MOV r1, 0

       // Now store the result and increment the pointer
       SBCO reg_mcasp_adc_data, C_MCASP_MEM, reg_mcasp_adc_current, 4
       ADD reg_mcasp_adc_current, reg_mcasp_adc_current, 4
 MCASP_ADC_DONE:	
       QBBC SPI_SKIP_WRITE, reg_flags, FLAG_BIT_USE_SPI
-	
+
       // DAC: transmit low word (first in little endian)
       MOV r2, 0xFFFF
       AND r7, reg_dac_data, r2
       LSL r7, r7, AD5668_DATA_OFFSET
       MOV r8, (0x03 << AD5668_COMMAND_OFFSET)

       // Repeat 4 times for 8 channels (2 samples per loop, r1 += 1 already happened)
       // For 4 or 2 channels, repeat 2 or 1 times, according to flags
       ADD r1, r1, 1
       QBNE ADC_DAC_LOOP, r1, reg_num_channels
       QBA ADC_DAC_LOOP_DONE
-
 SPI_SKIP_WRITE:
       // We get here only if the SPI ADC and DAC are disabled
       // Just keep the loop going for McASP
 
       // Toggle the high/low word for McASP control (since we send one word out of

       LBBO r2, reg_comm_addr, COMM_LED_PIN_MASK, 4
       MOV r1, GPIO_CLEARDATAOUT
       ADD r3, r3, r1          // Address for GPIO clear register
       SBBO r2, r3, 0, 4       // Clear GPIO pin	
 LED_BLINK_DONE:	
-	
       // Check if we should finish: flag is zero as long as it should run
       LBBO r2, reg_comm_addr, COMM_SHOULD_STOP, 4
       QBEQ WRITE_ONE_BUFFER, r2, 0
 
 CLEANUP:

       MOV r3, SPI_BASE + SPI_CH0CTRL
       LBBO r2, r3, 0, 4
       CLR r2, r2, 1
       SBBO r2, r3, 0, 4      
 SPI_CLEANUP_DONE:
-	
       // Signal the ARM that we have finished 
       MOV R31.b0, PRU0_ARM_INTERRUPT + 16
       HALT