comparison pru_rtaudio.p @ 253:33e0e4831763 prerelease

Started prerelease branch; updated PRU code to be able to run on either PRU.

 #define COMM_LED_ADDRESS      24          // Which memory address to find the status LED on
 #define COMM_LED_PIN_MASK     28          // Which pin to write to change LED
 #define COMM_FRAME_COUNT      32	  // How many frames have elapse since beginning
 #define COMM_USE_SPI          36          // Whether or not to use SPI ADC and DAC
 #define COMM_NUM_CHANNELS     40	  // Low 2 bits indicate 8 [0x3], 4 [0x1] or 2 [0x0] channels
-#define COMM_USE_DIGITAL  44	  // Whether or not to use DIGITAL
+#define COMM_USE_DIGITAL      44	  // Whether or not to use DIGITAL
+#define COMM_PRU_NUMBER       48          // Which PRU this code is running on
 
 #define MCASP0_BASE 0x48038000
 #define MCASP1_BASE 0x4803C000
 
 #define MCASP_PWRIDLESYSCONFIG 		0x04

      AND r28, r28, r27
      QBEQ POLL, r28, 0
 .endm
    
 START:
-     // Set up c24 and c25 offsets with CTBIR register
-     // Thus C24 points to start of PRU0 RAM
-     MOV r3, 0x22020       // CTBIR0
-     MOV r2, 0
-     SBBO r2, r3, 0, 4
-
-     // Set up c28 pointer offset for shared PRU RAM
-     MOV r3, 0x22028       // CTPPR0
-     MOV r2, 0x00000120    // To get address 0x00012000
-     SBBO r2, r3, 0, 4
-	
      // Load useful registers for addressing SPI
      MOV reg_comm_addr, SHARED_COMM_MEM_BASE
      MOV reg_spi_addr, SPI_BASE
      MOV reg_mcasp_addr, MCASP_BASE
+
+     // Find out which PRU we are running on
+     // This affects the following offsets
+     MOV  r0, 0x24000      // PRU1 control register offset
+     LBBO r2, reg_comm_addr, COMM_PRU_NUMBER, 4
+     QBEQ PRU_NUMBER_CHECK_DONE, r2, 1
+     MOV  r0, 0x22000      // PRU0 control register offset
+PRU_NUMBER_CHECK_DONE:	
+	
+     // Set up c24 and c25 offsets with CTBIR register
+     // Thus C24 points to start of PRU0 RAM
+     OR  r3, r0, 0x20      // CTBIR0
+     MOV r2, 0
+     SBBO r2, r3, 0, 4
+
+     // Set up c28 pointer offset for shared PRU RAM
+     OR r3, r0, 0x28       // CTPPR0
+     MOV r2, 0x00000120    // To get address 0x00012000
+     SBBO r2, r3, 0, 4
 	
      // Set ARM such that PRU can write to registers
      LBCO r0, C4, 4, 4
      CLR r0, r0, 4
      SBCO r0, C4, 4, 4