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d@0:d@0: d@0: Previous: Cell Caveats, d@0: Up: FFTW on the Cell Processor d@0:
The SPEs are fully IEEE-754 compliant in double precision. In single d@0: precision, they only implement round-towards-zero as opposed to the d@0: standard round-to-even mode. (The PPE is fully IEEE-754 compliant d@0: like all other PowerPC implementations.) Because of the rounding d@0: mode, FFTW is less accurate when running on the SPEs than on the PPE. d@0: The accuracy loss is hard to quantify in general, but as a rough d@0: guideline, the L2 norm of the relative roundoff error for random d@0: inputs is 4 to 8 times larger than the corresponding calculation in d@0: round-to-even arithmetic. In other words, expect to lose 2 to 3 bits d@0: of accuracy. d@0: d@0:
FFTW currently does not use any algorithm that degrades accuracy to d@0: gain performance on the SPE. One implication of this choice is that d@0: large 1D transforms run slower than they would if we were willing to d@0: sacrifice another bit or so of accuracy. d@0: d@0: d@0: d@0: